Lines Matching defs:CPol
1097 case ImmTyCPol: OS << "CPol"; break;
1797 const unsigned CPol);
5003 unsigned CPol = Inst.getOperand(CPolPos).getImm();
5006 return validateTHAndScopeBits(Inst, Operands, CPol);
5010 if (CPol && (isSI() || isCI())) {
5015 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) {
5021 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
5039 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {
5045 if (CPol & CPol::GLC) {
5061 const unsigned CPol) {
5062 const unsigned TH = CPol & AMDGPU::CPol::TH;
5063 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE;
5076 (!(TH & AMDGPU::CPol::TH_ATOMIC_RETURN)))
5083 ((TH == AMDGPU::CPol::TH_NT_RT) || (TH == AMDGPU::CPol::TH_RT_NT) ||
5084 (TH == AMDGPU::CPol::TH_NT_HT)))
5087 if (TH == AMDGPU::CPol::TH_BYPASS) {
5088 if ((Scope != AMDGPU::CPol::SCOPE_SYS &&
5089 CPol & AMDGPU::CPol::TH_REAL_BYPASS) ||
5090 (Scope == AMDGPU::CPol::SCOPE_SYS &&
5091 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS)))
5100 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC))
5103 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE))
5106 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD))
6601 .Case("nt", AMDGPU::CPol::NT)
6602 .Case("sc0", AMDGPU::CPol::SC0)
6603 .Case("sc1", AMDGPU::CPol::SC1)
6608 .Case("dlc", AMDGPU::CPol::DLC)
6609 .Case("glc", AMDGPU::CPol::GLC)
6610 .Case("scc", AMDGPU::CPol::SCC)
6611 .Case("slc", AMDGPU::CPol::SLC)
6663 unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);
6664 if (!CPol)
6669 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)
6672 if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)
6675 if (Seen & CPol)
6679 Enabled |= CPol;
6681 Seen |= CPol;
6694 static const unsigned Scopes[] = {CPol::SCOPE_CU, CPol::SCOPE_SE,
6695 CPol::SCOPE_DEV, CPol::SCOPE_SYS};
6708 TH = AMDGPU::CPol::TH_RT; // default
6717 TH = AMDGPU::CPol::TH_RT;
6722 TH = AMDGPU::CPol::TH_TYPE_ATOMIC;
6724 TH = AMDGPU::CPol::TH_TYPE_LOAD;
6726 TH = AMDGPU::CPol::TH_TYPE_STORE;
6732 TH |= AMDGPU::CPol::TH_REAL_BYPASS;
6735 if (TH & AMDGPU::CPol::TH_TYPE_ATOMIC)
6737 .Case("RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN)
6738 .Case("RT", AMDGPU::CPol::TH_RT)
6739 .Case("RT_RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN)
6740 .Case("NT", AMDGPU::CPol::TH_ATOMIC_NT)
6741 .Case("NT_RETURN", AMDGPU::CPol::TH_ATOMIC_NT |
6742 AMDGPU::CPol::TH_ATOMIC_RETURN)
6743 .Case("CASCADE_RT", AMDGPU::CPol::TH_ATOMIC_CASCADE)
6744 .Case("CASCADE_NT", AMDGPU::CPol::TH_ATOMIC_CASCADE |
6745 AMDGPU::CPol::TH_ATOMIC_NT)
6749 .Case("RT", AMDGPU::CPol::TH_RT)
6750 .Case("NT", AMDGPU::CPol::TH_NT)
6751 .Case("HT", AMDGPU::CPol::TH_HT)
6752 .Case("LU", AMDGPU::CPol::TH_LU)
6753 .Case("RT_WB", AMDGPU::CPol::TH_RT_WB)
6754 .Case("NT_RT", AMDGPU::CPol::TH_NT_RT)
6755 .Case("RT_NT", AMDGPU::CPol::TH_RT_NT)
6756 .Case("NT_HT", AMDGPU::CPol::TH_NT_HT)
6757 .Case("NT_WB", AMDGPU::CPol::TH_NT_WB)
6758 .Case("BYPASS", AMDGPU::CPol::TH_BYPASS)