Lines Matching defs:AMDGPUAsmParser
1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
51 class AMDGPUAsmParser;
68 const AMDGPUAsmParser *AsmParser;
71 AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
1174 static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,
1189 static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,
1200 static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
1210 static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,
1264 // Instruction will error in AMDGPUAsmParser::matchAndEmitInstruction
1317 class AMDGPUAsmParser : public MCTargetAsmParser {
1418 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
1575 return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
1723 bool Error(AMDGPUAsmParser &Parser, const Twine &Err) const {
1728 virtual bool validate(AMDGPUAsmParser &Parser) const {
2292 const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(),
2523 void AMDGPUAsmParser::createConstantSymbol(StringRef Id, int64_t Val) {
2690 bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
2701 bool AMDGPUAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
2706 ParseStatus AMDGPUAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
2718 bool AMDGPUAsmParser::AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
2802 AMDGPUAsmParser::isRegister(const AsmToken &Token,
2837 AMDGPUAsmParser::isRegister()
2842 MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
2886 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
2928 MCRegister AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
2944 MCRegister AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
2985 MCRegister AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind,
3040 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind,
3074 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind,
3093 AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {
3104 void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {
3111 bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
3141 AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
3160 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
3256 ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
3268 ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
3279 AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3288 AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {
3293 AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3298 AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
3316 AMDGPUAsmParser::isModifier() {
3350 AMDGPUAsmParser::parseSP3NegModifier() {
3367 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
3436 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
3467 ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
3471 ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
3475 ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
3495 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3529 ArrayRef<unsigned> AMDGPUAsmParser::getMatchedVariants() const {
3558 StringRef AMDGPUAsmParser::getMatchedVariantName() const {
3577 unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
3598 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
3658 unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {
3715 bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
3746 bool AMDGPUAsmParser::validateConstantBusLimitations(
3835 bool AMDGPUAsmParser::validateVOPDRegBankConstraints(
3878 bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
3895 bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
3943 bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
4012 bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
4032 bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
4051 bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst,
4074 bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {
4112 bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,
4140 bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
4166 bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,
4188 bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
4254 bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
4282 bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
4429 AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
4462 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
4471 bool AMDGPUAsmParser::validateOffset(const MCInst &Inst,
4505 bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
4539 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
4549 bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
4581 bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
4617 bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
4654 bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
4693 bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
4735 bool AMDGPUAsmParser::validateVccOperand(MCRegister Reg) const {
4742 bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
4824 bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
4854 bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
4880 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {
4889 bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,
4921 bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,
4944 bool AMDGPUAsmParser::validateDS(const MCInst &Inst,
4969 bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
4995 bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
5059 bool AMDGPUAsmParser::validateTHAndScopeBits(const MCInst &Inst,
5113 bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
5128 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
5263 bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
5268 bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
5279 bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
5335 bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5404 bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
5416 bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
5436 bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
5440 bool AMDGPUAsmParser::calculateGPRBlocks(
5503 bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
5993 bool AMDGPUAsmParser::ParseDirectiveAMDHSACodeObjectVersion() {
6002 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
6045 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
6071 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
6083 bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
6100 bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
6116 bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
6153 bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {
6166 bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
6198 bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
6248 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
6294 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
6360 ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,
6413 StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
6447 bool AMDGPUAsmParser::parseInstruction(ParseInstructionInfo &Info,
6492 ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,
6502 ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,
6511 ParseStatus AMDGPUAsmParser::parseIntWithPrefix(
6529 ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(
6569 ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,
6595 unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
6615 ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
6692 ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands,
6707 ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
6770 AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,
6782 ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,
6793 ParseStatus AMDGPUAsmParser::parseStringOrIntWithPrefix(
6818 ParseStatus AMDGPUAsmParser::parseStringOrIntWithPrefix(
6835 bool AMDGPUAsmParser::tryParseFmt(const char *Pref,
6856 ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands,
6875 ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) {
6879 ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) {
6885 ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {
6917 ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {
6932 bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,
6955 ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,
6992 ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,
7008 ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {
7020 ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {
7047 ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
7098 ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
7108 ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
7116 ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
7130 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
7217 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
7265 ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
7284 bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {
7346 ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
7375 void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,
7395 bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
7433 ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
7460 ParseStatus AMDGPUAsmParser::parseHwregFunc(OperandInfoTy &HwReg,
7500 ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
7512 bool validate(AMDGPUAsmParser &Parser) const override {
7552 AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,
7589 AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,
7637 ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
7672 ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
7693 ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
7735 ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
7760 AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {
7765 AMDGPUAsmParser::isId(const StringRef Id) const {
7770 AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {
7774 StringRef AMDGPUAsmParser::getId() const {
7779 AMDGPUAsmParser::trySkipId(const StringRef Id) {
7788 AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {
7800 AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {
7810 AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {
7819 AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,
7829 AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {
7849 AMDGPUAsmParser::parseExpr(OperandVector &Operands) {
7866 AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
7877 AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
7889 AMDGPUAsmParser::getToken() const {
7893 AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {
7900 AMDGPUAsmParser::peekTokens(MutableArrayRef<AsmToken> Tokens) {
7908 AMDGPUAsmParser::getTokenKind() const {
7913 AMDGPUAsmParser::getLoc() const {
7918 AMDGPUAsmParser::getTokenStr() const {
7923 AMDGPUAsmParser::lex() {
7927 SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
7932 AMDGPUAsmParser::getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
7943 AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,
7949 SMLoc AMDGPUAsmParser::getRegLoc(MCRegister Reg,
7957 SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
7968 SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
7976 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
7984 AMDGPUAsmParser::parseStructuredOpFields(ArrayRef<StructuredOpField *> Fields) {
8018 bool AMDGPUAsmParser::validateStructuredOpFields(
8042 bool AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op, const unsigned MinVal,
8061 AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
8075 AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {
8091 AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {
8119 AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {
8141 AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {
8163 AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
8209 bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
8229 bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
8258 AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
8273 AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
8305 ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
8336 int64_t AMDGPUAsmParser::parseGPRIdxMacro() {
8380 ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
8411 ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
8441 ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
8449 void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
8544 bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {
8553 void AMDGPUAsmParser::onBeginOfFile() {
8571 bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
8623 ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
8675 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,
8681 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
8700 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
8738 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
8798 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
8848 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
8853 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
8973 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
8987 void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) {
9020 ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {
9041 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
9126 bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {
9155 ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {
9178 ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
9214 AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,
9239 AMDGPUAsmParser::parseDPPCtrlPerm() {
9269 AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {
9316 ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
9351 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
9464 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
9536 ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
9545 ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
9551 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
9555 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
9559 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
9563 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
9567 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
9571 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
9683 RegisterMCAsmParser<AMDGPUAsmParser> A(getTheR600Target());
9684 RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
9693 ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
9720 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
9781 ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {