Lines Matching defs:GCNPassConfig

1057 class GCNPassConfig final : public AMDGPUPassConfig {
1059   GCNPassConfig(TargetMachine &TM, PassManagerBase &PM)
1331 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1352 bool GCNPassConfig::addPreISel() {
1383 void GCNPassConfig::addMachineSSAOptimization() {
1407 bool GCNPassConfig::addILPOpts() {
1415 bool GCNPassConfig::addInstSelector() {
1422 bool GCNPassConfig::addIRTranslator() {
1427 void GCNPassConfig::addPreLegalizeMachineIR() {
1433 bool GCNPassConfig::addLegalizeMachineIR() {
1438 void GCNPassConfig::addPreRegBankSelect() {
1444 bool GCNPassConfig::addRegBankSelect() {
1454 void GCNPassConfig::addPreGlobalInstructionSelect() {
1459 bool GCNPassConfig::addGlobalInstructionSelect() {
1464 void GCNPassConfig::addFastRegAlloc() {
1478 void GCNPassConfig::addOptimizedRegAlloc() {
1515 bool GCNPassConfig::addPreRewrite() {
1521 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1536 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1551 FunctionPass *GCNPassConfig::createWWMRegAllocPass(bool Optimized) {
1566 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1574 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1600 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1642 void GCNPassConfig::addPostRegAlloc() {
1649 void GCNPassConfig::addPreSched2() {
1655 void GCNPassConfig::addPreEmitPass() {
1689   return new GCNPassConfig(*this, PM);