Lines Matching defs:Src1Regs

2142   SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2146     assert(Src0Regs.empty() && Src1Regs.empty());
2152   assert(Src0Regs.size() == Src1Regs.size() &&
2169   if (Src1Regs.empty())
2170     split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2172     setRegsToType(MRI, Src1Regs, HalfTy);
2194   Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0);
2195   Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0);
2197   Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0);
2199   B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]);
2363     SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2368       assert(Src1Regs.empty() && Src2Regs.empty());
2372     if (Src1Regs.empty())
2373       split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2375       setRegsToType(MRI, Src1Regs, HalfTy);
2386     B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0], Flags);
2387     B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1], Flags);
2441     SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2445       assert(Src0Regs.empty() && Src1Regs.empty());
2450     assert(Src0Regs.size() == Src1Regs.size() &&
2462     if (Src1Regs.empty())
2463       split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
2465       setRegsToType(MRI, Src1Regs, HalfTy);
2470     B.buildInstr(Opc, {DefRegs[0]}, {Src0Regs[0], Src1Regs[0]}, Flags);
2471     B.buildInstr(Opc, {DefRegs[1]}, {Src0Regs[1], Src1Regs[1]}, Flags);