Lines Matching defs:Src0Regs

2141   SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2146     assert(Src0Regs.empty() && Src1Regs.empty());
2152   assert(Src0Regs.size() == Src1Regs.size() &&
2153          (Src0Regs.empty() || Src0Regs.size() == 2));
2164   if (Src0Regs.empty())
2165     split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
2167     setRegsToType(MRI, Src0Regs, HalfTy);
2194   Register Hi = B.buildUMulH(HalfTy, Src0Regs[0], Src1Regs[0]).getReg(0);
2195   Register MulLoHi = B.buildMul(HalfTy, Src0Regs[0], Src1Regs[1]).getReg(0);
2197   Register MulHiLo = B.buildMul(HalfTy, Src0Regs[1], Src1Regs[0]).getReg(0);
2199   B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]);
2440     SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2445       assert(Src0Regs.empty() && Src1Regs.empty());
2450     assert(Src0Regs.size() == Src1Regs.size() &&
2451            (Src0Regs.empty() || Src0Regs.size() == 2));
2457     if (Src0Regs.empty())
2458       split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
2460       setRegsToType(MRI, Src0Regs, HalfTy);
2470     B.buildInstr(Opc, {DefRegs[0]}, {Src0Regs[0], Src1Regs[0]}, Flags);
2471     B.buildInstr(Opc, {DefRegs[1]}, {Src0Regs[1], Src1Regs[1]}, Flags);