Lines Matching defs:S32
133 const LLT S32 = LLT::scalar(32);
135 assert(MRI.getType(DstReg) == S32);
142 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
143 auto False = B.buildConstant(S32, 0);
721 LLT S32 = LLT::scalar(32);
729 auto Unmerge = B.buildUnmerge(S32, Src);
737 MRI.setType(DstPart, NumParts == 1 ? Ty : S32);
1096 const LLT S32 = LLT::scalar(32);
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0);
1260 const LLT S32 = LLT::scalar(32);
1267 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1268 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1288 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1296 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1331 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0);
1335 SOffsetReg = B.buildConstant(S32, 0).getReg(0);
1363 const LLT S32 = LLT::scalar(32);
1414 Register VIndex = B.buildConstant(S32, 0).getReg(0);
1488 const LLT S32 = LLT::scalar(32);
1498 if (Ty == S32)
1509 auto UnmergeSOffset = B.buildUnmerge({S32, S32}, ShiftOffset);
1516 auto Zero = B.buildConstant(S32, 0);
1522 Signed ? B.buildSbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg)
1523 : B.buildUbfx(S32, UnmergeSOffset.getReg(0), Zero, WidthReg);
1525 Signed ? B.buildAShr(S32, Extract, B.buildConstant(S32, 31)) : Zero;
1530 auto UpperWidth = B.buildConstant(S32, WidthImm - 32);
1533 ? B.buildSbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth)
1534 : B.buildUbfx(S32, UnmergeSOffset.getReg(1), Zero, UpperWidth);
1543 auto ExtShift = B.buildSub(S32, B.buildConstant(S32, 64), WidthReg);
1558 auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
1559 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
1562 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16));
1567 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
1571 unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) :
1601 LLT S32 = LLT::scalar(32);
1613 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0);
1619 DstHi = IsUnsigned ? B.buildUMulH(S32, Src0, Src1).getReg(0)
1620 : B.buildSMulH(S32, Src0, Src1).getReg(0);
1623 Register VSrc0 = B.buildCopy(S32, Src0).getReg(0);
1624 Register VSrc1 = B.buildCopy(S32, Src1).getReg(0);
1629 DstHi = IsUnsigned ? B.buildUMulH(S32, VSrc0, VSrc1).getReg(0)
1630 : B.buildSMulH(S32, VSrc0, VSrc1).getReg(0);
1647 LLT CarryType = DstOnValu ? S1 : S32;
1656 Zero = B.buildConstant(S32, 0).getReg(0);
1660 Carry = B.buildICmp(CmpInst::ICMP_SLT, MulHiInVgpr ? S1 : S32, DstHi, Zero)
1673 DstLo = B.buildCopy(S32, DstLo).getReg(0);
1674 DstHi = B.buildCopy(S32, DstHi).getReg(0);
1679 auto Unmerge = B.buildUnmerge(S32, Src2);
1693 auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo);
1699 auto AddHi = B.buildUAdde(S32, CarryType, DstHi, Src2Hi, CarryLo);
1751 const LLT S32 = LLT::scalar(32);
1752 auto Bitcast = B.buildBitcast(S32, Src);
1755 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16);
1756 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16));
1760 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16));
1762 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff));
1803 const LLT S32 = LLT::scalar(32);
1806 return B.buildMergeLikeInstr(LLT::fixed_vector(NumElts, S32), WideRegs)
1830 const LLT S32 = LLT::scalar(32);
1856 BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1858 auto OverflowVal = B.buildConstant(S32, Overflow);
1859 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1865 BaseReg = B.buildConstant(S32, 0).getReg(0);
1910 const LLT S32 = LLT::scalar(32);
1914 auto MaterializedOffset = B.buildConstant(S32, ConstOffset);
1916 auto Add = B.buildAdd(S32, WaterfallIdx, MaterializedOffset);
1971 LLT S32 = LLT::scalar(32);
1983 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
1986 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
2004 auto IC = B.buildConstant(S32, I);
2069 LLT S32 = LLT::scalar(32);
2084 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
2087 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
2105 auto IC = B.buildConstant(S32, I);
2249 const LLT S32 = LLT::scalar(32);
2284 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2313 const LLT S32 = LLT::scalar(32);
2314 Register NewDstReg = MRI.createGenericVirtualRegister(S32);
2319 Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
2349 const LLT S32 = LLT::scalar(32);
2350 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2400 const LLT S32 = LLT::scalar(32);
2401 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2525 const LLT S32 = LLT::scalar(32);
2535 auto Lo = B.buildInstr(AMDGPU::G_ABS, {S32}, {WideSrcLo});
2536 auto Hi = B.buildInstr(AMDGPU::G_ABS, {S32}, {WideSrcHi});
2551 auto Lo = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Lo, WideSrc1Lo});
2552 auto Hi = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Hi, WideSrc1Hi});
2558 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2565 if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2589 const LLT S32 = LLT::scalar(32);
2616 MRI.setType(Op0L, S32);
2622 MRI.setType(Op1L, S32);
2643 const LLT S32 = LLT::scalar(32);
2659 auto Freeze = B.buildFreeze(S32, SrcRegs[0]);
2664 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
2685 const LLT S32 = LLT::scalar(32);
2687 if (Ty == S32)
2695 if (Helper.narrowScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2709 const LLT S32 = LLT::scalar(32);
2711 if (Ty == S32)
2728 auto X = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx]});
2729 auto Y = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx ^ 1]});
2734 Y = B.buildInstr(AddOpc, {S32}, {Y, B.buildConstant(S32, 32)});
2829 const LLT S32 = LLT::scalar(32);
2895 auto One = B.buildConstant(S32, 1);
2906 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
2907 auto IdxHi = B.buildAdd(S32, IdxLo, One);
2933 Register TmpReg0 = MRI.createGenericVirtualRegister(S32);
2934 Register TmpReg1 = MRI.createGenericVirtualRegister(S32);
3006 const LLT S32 = LLT::scalar(32);
3010 auto One = B.buildConstant(S32, 1);
3019 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
3020 auto IdxHi = B.buildAdd(S32, IdxLo, One);