AMDGPURegisterBankInfo.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines Matching defs:DstBank
158       const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);
159       assert(DstBank != &AMDGPU::VCCRegBank);
1065   const RegisterBank *DstBank =
1067   if (DstBank == &AMDGPU::SGPRRegBank) {
1091     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);
1495   const RegisterBank *DstBank =
1497   if (DstBank == &AMDGPU::VGPRRegBank) {
1650   const RegisterBank &DstBank =
1682     MRI.setRegBank(Src2Lo, DstBank);
1683     MRI.setRegBank(Src2Hi, DstBank);
1696     MRI.setRegBank(DstLo, DstBank);
1701     MRI.setRegBank(DstHi, DstBank);
1973   const RegisterBank &DstBank =
1979     (DstBank == AMDGPU::SGPRRegBank &&
2014         MRI.setRegBank(S->getOperand(N).getReg(), DstBank);
2023     MRI.setRegBank(DstReg, DstBank);
2026   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);
2071   const RegisterBank &DstBank =
2079     (DstBank == AMDGPU::SGPRRegBank &&
2111       Register Op0 = constrainRegToBank(MRI, B, InsRegs[L], DstBank);
2113       Op1 = constrainRegToBank(MRI, B, Op1, DstBank);
2116       MRI.setRegBank(Select, DstBank);
2127     MRI.setRegBank(Vec->getOperand(0).getReg(), DstBank);
2131   MRI.setRegBank(MI.getOperand(0).getReg(), DstBank);
2219     const RegisterBank *DstBank =
2221     if (DstBank == &AMDGPU::VCCRegBank)
2239     MRI.setRegBank(NewDstReg, *DstBank);
2250     const RegisterBank *DstBank =
2252     if (DstBank == &AMDGPU::VCCRegBank) {
2280     ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);
2304     const RegisterBank *DstBank =
2306     if (DstBank != &AMDGPU::SGPRRegBank)
2420       const RegisterBank *DstBank =
2422       if (DstBank == &AMDGPU::VCCRegBank)
2426       ApplyRegBankMapping ApplyBank(B, *this, MRI, DstBank);
2520     const RegisterBank *DstBank =
2522     if (DstBank == &AMDGPU::VGPRRegBank)
2593     const RegisterBank *DstBank =
2598     if (DstBank == &AMDGPU::SGPRRegBank) {
2679     const RegisterBank *DstBank =
2681     if (DstBank == &AMDGPU::SGPRRegBank)
2703     const RegisterBank *DstBank =
2705     if (DstBank == &AMDGPU::SGPRRegBank)
2788       const RegisterBank *DstBank = &AMDGPU::VGPRRegBank;
2800       MRI.setRegBank(True.getReg(0), *DstBank);
2801       MRI.setRegBank(False.getReg(0), *DstBank);
2802       MRI.setRegBank(DstReg, *DstBank);
2809         MRI.setRegBank(Sel.getReg(0), *DstBank);
2838     const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank;
2865     const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank &&
2912     MRI.setRegBank(DstReg, *DstBank);
3025     const RegisterBank *DstBank =
3034     MRI.setRegBank(InsLo.getReg(0), *DstBank);
3035     MRI.setRegBank(InsHi.getReg(0), *DstBank);
3783     const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
3790     if (!SrcReg.isVirtual() && !DstBank &&
3792       DstBank = &AMDGPU::VCCRegBank;
3794       DstBank = &AMDGPU::VCCRegBank;
3796     if (!DstBank)
3797       DstBank = SrcBank;
3801         cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size)))
3804     const ValueMapping &ValMap = getValueMapping(0, Size, *DstBank);
3847     if (const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI))
3848       ResultBank = DstBank->getID();
3892       const RegisterBank *DstBank
3898       if (DstBank) {
3899         TargetBankID = DstBank->getID();
3900         if (DstBank == &AMDGPU::VCCRegBank) {
4235     unsigned DstBank;
4240       DstBank = AMDGPU::SGPRRegBankID;
4243       DstBank = AMDGPU::VGPRRegBankID;
4249     OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize);
4280     unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI,
4298     bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID &&
4303     DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;
4310     OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize);