Lines Matching defs:V2S16

300 static const LLT V2S16 = LLT::fixed_vector(2, 16);
341     V2S16, V4S16, V6S16, V8S16, V10S16, V12S16, V16S16, V2S128, V4S128};
698     S32, S64, S16, V2S16
709       .legalFor({S32, S64, V2S16, S16, V4S16, S1, S128, S256})
726           .legalFor({S64, S32, S16, V2S16})
734           .legalFor({S32, S16, V2S16})
744           .legalFor({S64, S32, S16, V2S16})
752           .legalFor({S32, S16, V2S16})
762       .legalFor({S32, S16, V2S16}) // Clamp modifier
863     .legalFor({S32, S1, S64, V2S32, S16, V2S16, V4S16})
933       FPOpActions.legalFor({S16, V2S16});
1046         {{S32, S64}, {S16, S32}, {V2S16, V2S32}, {V2S16, V2S64}});
1062       .lowerFor({S64, V2S16});
1068       .lowerFor({S64, S16, V2S16});
1098     .legalFor({{V2S16, V2S32}})
1320       .legalFor({S16, S32, V2S16})
1330         .legalFor({S32, S16, V2S16})
1451                                       {V2S16, GlobalPtr, V2S16, GlobalAlign32},
1460                                       {V2S16, LocalPtr, S32, 32},
1465                                       {V2S16, PrivatePtr, S32, 32},
1715       .legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16, GlobalPtr,
1737       Shifts.legalFor({{S16, S16}, {V2S16, V2S16}})
1884     .fewerElementsIf(isWideVec16(0), changeTo(0, V2S16))
1896       .legalFor({V2S16, S32})
1899     BuildVector.customFor({V2S16, S16});
1903       .customFor({V2S16, S32})
1937       .lowerFor({{S16, V2S16}})
1949                        changeTo(1, V2S16))
2002     SextInReg.lowerFor({{V2S16}})
2027     .lowerFor({{V2S16, V2S16}})
2034       .lowerFor({{V2S16, V2S16}})
6304   const LLT V2S16 = LLT::fixed_vector(2, 16);
6323             B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
6329         AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0);
6344             B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
6349                  V2S16, {AddrReg, MI.getOperand(ArgOffset + I + 1).getReg()})
6417   const LLT V2S16 = LLT::fixed_vector(2, 16);
6643   // Register type to use for each loaded component. Will be S32 or V2S16.
6658     RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
6729   if (Ty == V2S16 && NumDataRegs == 1 && !ST.hasUnpackedD16VMem()) {
6742     if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) {
6744         Reg = B.buildBitcast(V2S16, Reg).getReg(0);
6767   assert(!ST.hasUnpackedD16VMem() && ResTy == V2S16);
7028   const LLT V2S16 = LLT::fixed_vector(2, 16);
7097                 S32, B.buildMergeLikeInstr(V2S16, {UnmergeRayInvDir.getReg(0),
7101                 S32, B.buildMergeLikeInstr(V2S16, {UnmergeRayInvDir.getReg(1),
7105                 S32, B.buildMergeLikeInstr(V2S16, {UnmergeRayInvDir.getReg(2),