Lines Matching full:const
51 const GCNSubtarget *Subtarget;
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
59 static const char *getName();
72 bool isSGPR(Register Reg) const;
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectG_FMA_FMAD(MachineInstr &I) const;
105 bool selectG_MERGE_VALUES(MachineInstr &I) const;
106 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
107 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
108 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
109 bool selectG_INSERT(MachineInstr &I) const;
110 bool selectG_SBFX_UBFX(MachineInstr &I) const;
112 bool selectInterpP1F16(MachineInstr &MI) const;
113 bool selectWritelane(MachineInstr &MI) const;
114 bool selectDivScale(MachineInstr &MI) const;
115 bool selectIntrinsicCmp(MachineInstr &MI) const;
116 bool selectBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectInitWholeWave(MachineInstr &MI) const;
127 bool selectSBarrier(MachineInstr &MI) const;
128 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
131 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
132 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
133 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
134 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
135 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
136 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
137 SmallVectorImpl<GEPInfo> &AddrInfo) const;
139 void initM0(MachineInstr &I) const;
140 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
141 bool selectG_SELECT(MachineInstr &I) const;
142 bool selectG_BRCOND(MachineInstr &I) const;
143 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
144 bool selectG_PTRMASK(MachineInstr &I) const;
145 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
147 bool selectBufferLoadLds(MachineInstr &MI) const;
148 bool selectGlobalLoadLds(MachineInstr &MI) const;
149 bool selectBVHIntrinsic(MachineInstr &I) const;
150 bool selectSMFMACIntrin(MachineInstr &I) const;
151 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
152 bool selectWaveAddress(MachineInstr &I) const;
153 bool selectBITOP3(MachineInstr &I) const;
154 bool selectStackRestore(MachineInstr &MI) const;
155 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
156 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
159 bool selectSBarrierLeave(MachineInstr &I) const;
164 bool OpSel = false) const;
168 bool ForceVGPR = false) const;
171 selectVCSRC(MachineOperand &Root) const;
174 selectVSRC0(MachineOperand &Root) const;
177 selectVOP3Mods0(MachineOperand &Root) const;
179 selectVOP3BMods0(MachineOperand &Root) const;
181 selectVOP3OMods(MachineOperand &Root) const;
183 selectVOP3Mods(MachineOperand &Root) const;
185 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
187 selectVOP3BMods(MachineOperand &Root) const;
189 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
192 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
193 bool IsDOT = false) const;
196 selectVOP3PMods(MachineOperand &Root) const;
199 selectVOP3PModsDOT(MachineOperand &Root) const;
202 selectVOP3PModsNeg(MachineOperand &Root) const;
205 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
208 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
210 selectWMMAModsF16Neg(MachineOperand &Root) const;
212 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
214 selectWMMAVISrc(MachineOperand &Root) const;
216 selectSWMMACIndex8(MachineOperand &Root) const;
218 selectSWMMACIndex16(MachineOperand &Root) const;
221 selectVOP3OpSelMods(MachineOperand &Root) const;
224 selectVINTERPMods(MachineOperand &Root) const;
226 selectVINTERPModsHi(MachineOperand &Root) const;
229 int64_t *Offset) const;
231 selectSmrdImm(MachineOperand &Root) const;
233 selectSmrdImm32(MachineOperand &Root) const;
235 selectSmrdSgpr(MachineOperand &Root) const;
237 selectSmrdSgprImm(MachineOperand &Root) const;
240 uint64_t FlatVariant) const;
243 selectFlatOffset(MachineOperand &Root) const;
245 selectGlobalOffset(MachineOperand &Root) const;
247 selectScratchOffset(MachineOperand &Root) const;
250 selectGlobalSAddr(MachineOperand &Root) const;
253 selectScratchSAddr(MachineOperand &Root) const;
255 uint64_t ImmOffset) const;
257 selectScratchSVAddr(MachineOperand &Root) const;
260 selectMUBUFScratchOffen(MachineOperand &Root) const;
262 selectMUBUFScratchOffset(MachineOperand &Root) const;
264 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
266 unsigned Size) const;
267 bool isFlatScratchBaseLegal(Register Addr) const;
268 bool isFlatScratchBaseLegalSV(Register Addr) const;
269 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
272 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
274 selectDS1Addr1Offset(MachineOperand &Root) const;
277 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
280 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
283 unsigned size) const;
285 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
289 const MachineRegisterInfo &MRI) const;
299 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
302 Register &SOffset, int64_t &ImmOffset) const;
304 MUBUFAddressData parseMUBUFAddress(Register Src) const;
308 int64_t &Offset) const;
311 Register &SOffset, int64_t &Offset) const;
314 selectBUFSOffset(MachineOperand &Root) const;
317 selectMUBUFAddr64(MachineOperand &Root) const;
320 selectMUBUFOffset(MachineOperand &Root) const;
322 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
323 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
324 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
327 bool &Matched) const;
328 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
329 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
331 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
332 int OpIdx = -1) const;
334 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
335 int OpIdx) const;
336 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
337 int OpIdx) const;
339 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
340 int OpIdx) const;
343 const MachineInstr &MI,
344 int OpIdx) const;
347 const MachineInstr &MI,
348 int OpIdx) const;
351 const MachineInstr &MI,
352 int OpIdx) const;
355 const MachineInstr &MI,
356 int OpIdx) const;
359 const MachineInstr &MI, int OpIdx) const;
362 const MachineInstr &MI, int OpIdx) const;
365 const MachineInstr &MI,
366 int OpIdx) const;
369 const MachineInstr &MI, int OpIdx) const;
371 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
372 int OpIdx) const;
374 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
375 int OpIdx) const;
377 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
378 int OpIdx) const {
381 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
382 int OpIdx) const {
386 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
387 int OpIdx) const;
388 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
389 int OpIdx) const;
390 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
391 int OpIdx) const;
392 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
393 int OpIdx) const;
395 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
396 int OpIdx) const;
398 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
399 int OpIdx) const;
401 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
402 int OpIdx) const;
404 const MachineInstr &MI, int OpIdx) const;
406 bool isInlineImmediate(const APInt &Imm) const;
407 bool isInlineImmediate(const APFloat &Imm) const;
411 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
413 const SIInstrInfo &TII;
414 const SIRegisterInfo &TRI;
415 const AMDGPURegisterBankInfo &RBI;
416 const AMDGPUTargetMachine &TM;
417 const GCNSubtarget &STI;