Lines Matching defs:SrcSize

596   const unsigned SrcSize = SrcTy.getSizeInBits();
616       TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank);
641   const unsigned SrcSize = SrcTy.getSizeInBits();
642   if (SrcSize < 32)
653   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
686   const unsigned SrcSize = SrcTy.getSizeInBits();
691       TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank);
726   const unsigned SrcSize = SrcTy.getSizeInBits();
729   if (MI.getOpcode() == AMDGPU::G_BUILD_VECTOR && SrcSize >= 32) {
2407   unsigned SrcSize = SrcTy.getSizeInBits();
2410       TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB);
2422   if (DstRC == &AMDGPU::VGPR_16RegClass && SrcSize == 32) {
2497   if (SrcSize > 32) {
2553   const unsigned SrcSize = I.getOpcode() == AMDGPU::G_SEXT_INREG ?
2591     if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
2605       .addImm(SrcSize); // Width
2616     if (Signed && DstSize == 32 && (SrcSize == 8 || SrcSize == 16)) {
2617       const unsigned SextOpc = SrcSize == 8 ?
2627     if (DstSize > 32 && SrcSize == 32) {
2653     if (DstSize > 32 && (SrcSize <= 32 || InReg)) {
2668         .addImm(SrcSize << 16);
2675     if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
2683         .addImm(SrcSize << 16);