Lines Matching defs:PtrBase

1925   Register PtrBase = MI.getOperand(2).getReg();
1926   LLT PtrTy = MRI->getType(PtrBase);
1930   std::tie(PtrBase, Offset) = selectDS1Addr1OffsetImpl(MI.getOperand(2));
1933   if (!isDSOffsetLegal(PtrBase, Offset)) {
1934     PtrBase = MI.getOperand(2).getReg();
1943     .addReg(PtrBase);
1944   if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI))
4776   Register PtrBase;
4778   std::tie(PtrBase, ConstOffset) =
4789   return std::pair(PtrBase, ConstOffset);
4826   Register PtrBase;
4832   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
4837       Addr = PtrBase;
4840       auto PtrBaseDef = getDefSrcRegIgnoringCopies(PtrBase, *MRI);
4863                 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, // saddr
4937   Register PtrBase;
4943   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
4948     Addr = PtrBase;
5013   Register PtrBase;
5019   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
5024     Addr = PtrBase;
5112   Register PtrBase;
5114   std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(VAddr, *MRI);
5118          KB->signBitIsZero(PtrBase))) {
5119       const MachineInstr *PtrBaseDef = MRI->getVRegDef(PtrBase);
5123         VAddr = PtrBase;
5351   Register PtrBase;
5353   std::tie(PtrBase, Offset) =
5357     if (isDSOffsetLegal(PtrBase, Offset)) {
5359       return std::pair(PtrBase, Offset);
5413   Register PtrBase;
5415   std::tie(PtrBase, Offset) =
5421     if (isDSOffset2Legal(PtrBase, OffsetValue0, OffsetValue1, Size)) {
5423       return std::pair(PtrBase, OffsetValue0 / Size);
5527   Register PtrBase;
5530   std::tie(PtrBase, Offset) = getPtrBaseWithConstantOffset(Src, *MRI);
5532     Data.N0 = PtrBase;