Lines Matching defs:Mods
4123 unsigned Mods = 0;
4128 Mods |= SISrcMods::NEG;
4136 Mods |= SISrcMods::NEG;
4143 Mods |= SISrcMods::ABS;
4147 Mods |= SISrcMods::OP_SEL_0;
4149 return std::pair(Src, Mods);
4153 Register Src, unsigned Mods, MachineOperand Root, MachineInstr *InsertPt,
4155 if ((Mods != 0 || ForceVGPR) &&
4184 unsigned Mods;
4185 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
4189 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
4191 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4200 unsigned Mods;
4201 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg(),
4207 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
4209 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4227 unsigned Mods;
4228 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
4232 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
4234 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4242 unsigned Mods;
4243 std::tie(Src, Mods) =
4248 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
4250 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4257 unsigned Mods;
4258 std::tie(Src, Mods) =
4264 MIB.addReg(copyToVGPRIfSrcFolded(Src, Mods, Root, MIB));
4266 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4284 unsigned Mods = 0;
4291 Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
4302 Mods |= SISrcMods::OP_SEL_1;
4304 return std::pair(Src, Mods);
4313 unsigned Mods;
4314 std::tie(Src, Mods) = selectVOP3PModsImpl(Root.getReg(), MRI);
4318 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4328 unsigned Mods;
4329 std::tie(Src, Mods) = selectVOP3PModsImpl(Root.getReg(), MRI, true);
4333 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4344 unsigned Mods = SISrcMods::OP_SEL_1;
4346 Mods ^= SISrcMods::NEG;
4348 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4357 unsigned Mods = SISrcMods::OP_SEL_1;
4359 Mods |= SISrcMods::OP_SEL_0;
4362 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4394 static void selectWMMAModsNegAbs(unsigned ModOpcode, unsigned &Mods,
4399 Mods |= SISrcMods::NEG;
4413 Mods |= SISrcMods::NEG_HI;
4419 Mods |= SISrcMods::NEG_HI;
4427 unsigned Mods = SISrcMods::OP_SEL_1;
4446 selectWMMAModsNegAbs(ModOpcode, Mods, EltsF32, Src, Root.getParent(),
4452 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4458 unsigned Mods = SISrcMods::OP_SEL_1;
4471 Mods |= SISrcMods::NEG;
4472 Mods |= SISrcMods::NEG_HI;
4478 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4484 unsigned Mods = SISrcMods::OP_SEL_1;
4505 selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
4511 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
4585 unsigned Mods;
4586 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
4591 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
4598 unsigned Mods;
4599 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg(),
4607 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4609 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
4616 unsigned Mods;
4617 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg(),
4625 copyToVGPRIfSrcFolded(Src, Mods, Root, MIB, /* ForceVGPR */ true));
4627 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
5799 unsigned Mods;
5800 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
5813 if ((Mods & SISrcMods::ABS) == 0) {
5818 Mods ^= SISrcMods::NEG;
5821 Mods |= SISrcMods::ABS;
5832 Mods |= SISrcMods::OP_SEL_1;
5835 Mods |= SISrcMods::OP_SEL_0;
5842 return {Src, Mods};
5849 unsigned Mods;
5851 std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
5857 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
5864 unsigned Mods;
5866 std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
5870 [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods