Lines Matching defs:IdxReg

3166                         const TargetRegisterClass *SuperRC, Register IdxReg,
3172       AMDGPU::getBaseWithConstantOffset(MRI, IdxReg, &KnownBits);
3177     IdxBaseReg = IdxReg;
3185     return std::pair(IdxReg, SubRegs[0]);
3193   Register IdxReg = MI.getOperand(2).getReg();
3200   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);
3215       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))
3223   std::tie(IdxReg, SubReg) = computeIndirectRegIndex(
3224       *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KB);
3231       .addReg(IdxReg);
3246       .addReg(IdxReg);
3258       .addReg(IdxReg)
3271   Register IdxReg = MI.getOperand(3).getReg();
3280   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);
3297       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))
3304   std::tie(IdxReg, SubReg) =
3305       computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, ValSize / 8, *KB);
3315       .addReg(IdxReg);
3332       .addReg(IdxReg)
3407     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());
3408     BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg)
3414     MIB.addReg(IdxReg);