Lines Matching defs:AddrDef

3513     auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
3514     if (isSGPR(AddrDef->Reg)) {
3515       Addr = AddrDef->Reg;
3516     } else if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
3518           getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
3520         Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
4887   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
4888   if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
4891         getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI);
4894       Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg();
4914   if (AddrDef->MI->getOpcode() == AMDGPU::G_IMPLICIT_DEF ||
4915       AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg))
4928       [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr
4952   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
4953   if (AddrDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
4954     int FI = AddrDef->MI->getOperand(1).getIndex();
4961   Register SAddr = AddrDef->Reg;
4963   if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
4964     Register LHS = AddrDef->MI->getOperand(1).getReg();
4965     Register RHS = AddrDef->MI->getOperand(2).getReg();
5028   auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
5029   if (AddrDef->MI->getOpcode() != AMDGPU::G_PTR_ADD)
5032   Register RHS = AddrDef->MI->getOperand(2).getReg();
5036   Register LHS = AddrDef->MI->getOperand(1).getReg();