AMDGPUISelLowering.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines Matching defs:AMDGPUTargetLowering
40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
55 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
61 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
635 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {
762 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
788 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
799 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
803 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
809 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
817 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
822 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
862 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
886 bool AMDGPUTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
890 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
894 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode *N) const {
918 SDValue AMDGPUTargetLowering::getNegatedExpression(
953 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
961 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
968 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
974 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
986 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
995 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
1007 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
1017 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
1029 bool AMDGPUTargetLowering::isNarrowingProfitable(SDNode *N, EVT SrcVT,
1070 bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(
1196 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
1310 SDValue AMDGPUTargetLowering::LowerReturn(
1327 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1332 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1337 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1371 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1398 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1403 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1414 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1462 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1502 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1554 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1589 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1642 SDValue AMDGPUTargetLowering::combineFMinMaxLegacyImpl(
1711 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1750 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1764 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1772 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1784 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1799 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1814 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1874 SDValue AMDGPUTargetLowering::WidenOrSplitVectorLoad(SDValue Op,
1908 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1952 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
2067 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
2281 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
2336 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
2397 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2411 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2451 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2497 SDValue AMDGPUTargetLowering::LowerFROUNDEVEN(SDValue Op,
2525 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op,
2534 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2545 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2572 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2621 bool AMDGPUTargetLowering::allowApproxFunc(const SelectionDAG &DAG,
2629 bool AMDGPUTargetLowering::needsDenormHandlingF32(const SelectionDAG &DAG,
2638 SDValue AMDGPUTargetLowering::getIsLtSmallestNormal(SelectionDAG &DAG,
2656 SDValue AMDGPUTargetLowering::getIsFinite(SelectionDAG &DAG, SDValue Src,
2673 AMDGPUTargetLowering::getScaledLogInput(SelectionDAG &DAG, const SDLoc SL,
2696 SDValue AMDGPUTargetLowering::LowerFLOG2(SDValue Op, SelectionDAG &DAG) const {
2737 SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
2834 SDValue AMDGPUTargetLowering::LowerFLOG10(SDValue Op, SelectionDAG &DAG) const {
2840 SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL,
2879 SDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const {
2930 SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue X, const SDLoc &SL,
2970 SDValue AMDGPUTargetLowering::lowerFEXP10Unsafe(SDValue X, const SDLoc &SL,
3022 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
3163 SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
3193 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
3253 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
3379 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
3398 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
3444 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
3493 SDValue AMDGPUTargetLowering::LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG,
3568 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
3667 SDValue AMDGPUTargetLowering::LowerFP_TO_INT(const SDValue Op,
3711 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
3739   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
3746          AMDGPUTargetLowering::numBitsSigned(Op, DAG) <= 24;
3827 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
3848 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
3901 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
3958 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
3981 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
4017 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
4040 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
4108 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
4143 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
4191 SDValue AMDGPUTargetLowering::performTruncateCombine(
4310 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
4395 AMDGPUTargetLowering::performMulLoHiCombine(SDNode *N,
4444 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
4477 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
4510 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
4537 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
4594 AMDGPUTargetLowering::foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
4604     if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
4652       if (!AMDGPUTargetLowering::allUsesHaveSourceMods(N.getNode()))
4671 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
4730 AMDGPUTargetLowering::getConstantNegateCost(const ConstantFPSDNode *C) const {
4740 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
4746 bool AMDGPUTargetLowering::isConstantCheaperToNegate(SDValue N) const {
4777 bool AMDGPUTargetLowering::shouldFoldFNegIntoSrc(SDNode *N, SDValue N0) {
4796 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
5058 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
5083 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
5095 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
5342 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
5378 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
5394 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
5413 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
5434 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
5453 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
5461 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
5617 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
5635 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
5669 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
5834 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
5895 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
5932 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
6046 bool AMDGPUTargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,