Lines Matching defs:VALU

68   VALU = 1u << 1,
78   ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
247 // {VMEM_READ, VALU, MFMA, VMEM_READ} and we encounter a VMEM_READ instruction
1603         SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII);
1616         SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII);
1656           SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII);
1670           SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII);
1747           SchedGroupMask::VALU, VALUOps, PipelineSyncID, DAG, TII);
1769             SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII);
1791             SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII);
1918       // Does the VALU have a DS_WRITE successor
1933       // Does the VALU have a DS_WRITE successor that is the same as other
1934       // VALU already in the group. The V_PERMs will all share 1 DS_W succ
1963       // Does the previous VALU have this DS_Write as a successor
2174   // For kernels with V_PERM, there are enough VALU to mix in between MFMAs
2182           SchedGroupMask::VALU, 2, PipelineSyncID, DAG, TII);
2218         SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII);
2275         SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII);
2289         SchedGroupMask::VALU, 4, PipelineSyncID, DAG, TII);
2416   else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) &&
2637   // ALU implies VALU, SALU, MFMA, TRANS.
2639     InvertedMask &= ~SchedGroupMask::VALU & ~SchedGroupMask::SALU &
2641   // VALU, SALU, MFMA, TRANS implies ALU.
2642   else if ((InvertedMask & SchedGroupMask::VALU) == SchedGroupMask::NONE ||