Lines Matching defs:STM
161 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
165 if (STM.requiresCodeObjectV6() && CodeObjectVersion < AMDGPU::AMDHSA_COV6) {
167 STM.getCPU() + " is only available on code object version 6 or better",
176 const auto &FunctionTargetID = STM.getTargetID();
199 if (STM.isMesaKernel(F) &&
204 KernelCode.validate(&STM, MF->getContext());
208 if (STM.isAmdHsaOS())
233 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
238 STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
273 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
274 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
364 const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
378 STM.getMaxWaveScratchSize() / STM.getWavefrontSize();
394 if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
395 !STM.hasSGPRInitBug()) {
396 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
424 &STM, VCCUsed, FlatUsed,
426 if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
427 STM.hasSGPRInitBug()) {
428 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
453 getTotalNumVGPRs(STM.hasGFX90AInsts(), NumAgpr, NumVgpr);
455 {TotalNumVgpr, (uint64_t)1, (uint64_t)STM.getMinNumVGPRs(MaxWaves)});
457 {NumSgpr, (uint64_t)1, (uint64_t)STM.getMinNumSGPRs(MaxWaves)});
459 STM.getOccupancyWithWorkGroupSizes(*MF).second,
461 MCConstantExpr::create(NumVGPRsForWavesPerEU, OutContext), STM,
604 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
617 STM.getKernArgSegmentSize(F, MaxKernArgAlign), Ctx);
619 KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM, Ctx);
628 assert(STM.hasGFX90AInsts() || !EvaluatableRsrc3 ||
633 AMDGPU::hasKernargPreload(STM) ? Info->getNumKernargPreloadedSGPRs() : 0,
657 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
661 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
675 if (STM.isAmdPalOS()) {
680 } else if (!STM.isAmdHsaOS()) {
685 if (STM.dumpCode()) {
700 STM.hasMAIInsts());
738 STM.hasMAIInsts()
758 STM.hasMAIInsts() ? CurrentProgramInfo.NumAccVGPR : nullptr,
785 if (STM.hasGFX90AInsts()) {
824 assert(STM.hasGFX90AInsts() ||
828 if (STM.hasGFX90AInsts()) {
885 const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
886 const IsaInfo::AMDGPUTargetID &STMTargetID = STM.getTargetID();
897 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
898 const SIInstrInfo *TII = STM.getInstrInfo();
937 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
968 ProgInfo.TgSplit = STM.isTgSplitEnabled();
987 if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
988 !STM.hasSGPRInitBug()) {
989 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
1014 F.getCallingConv() == CallingConv::AMDGPU_PS && !STM.isAmdHsaOS();
1099 CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
1103 CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
1106 if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
1107 STM.hasSGPRInitBug()) {
1108 unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
1124 if (STM.hasSGPRInitBug()) {
1131 if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
1135 STM.getMaxNumUserSGPRs(), DS_Error);
1140 static_cast<unsigned>(STM.getAddressableLocalMemorySize())) {
1144 STM.getAddressableLocalMemorySize(), DS_Error);
1163 IsaInfo::getSGPREncodingGranule(&STM));
1165 IsaInfo::getVGPREncodingGranule(&STM));
1179 if (STM.getFeatureBits().test(FeatureAddressableLocalMemorySize163840)) {
1182 } else if (STM.getFeatureBits().test(
1207 STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? 8 : 10;
1213 CreateExpr(STM.getWavefrontSize()), Ctx),
1217 ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1241 STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled();
1249 ProgInfo.LdsSize = STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks;
1252 if (STM.hasGFX90AInsts()) {
1275 STM.computeOccupancy(F, ProgInfo.LDSSize).second,
1276 ProgInfo.NumSGPRsForWavesPerEU, ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);
1308 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1331 EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc1(STM, Ctx),
1341 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) {
1345 } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) {
1369 if (STM.getGeneration() >= AMDGPUSubtarget::GFX12) {
1373 } else if (STM.getGeneration() == AMDGPUSubtarget::GFX11) {
1386 unsigned ExtraLDSSize = STM.getGeneration() >= AMDGPUSubtarget::GFX11
1439 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1440 if (STM.hasMAIInsts()) {
1446 MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC, STM, Ctx), Ctx);
1460 EmitPALMetadataCommon(MD, CurrentProgramInfo, CC, STM);
1471 unsigned ExtraLDSSize = STM.getGeneration() >= AMDGPUSubtarget::GFX11
1484 STM.getGeneration() >= AMDGPUSubtarget::GFX11 ? 256 : 128;
1511 if (MD->getPALMajorVersion() < 3 && STM.isWave32())
1562 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1565 Out.initDefault(&STM, Ctx, /*InitMCExpr=*/false);
1568 CurrentProgramInfo.getComputePGMRSrc1(STM, Ctx);
1576 getElementByteSizeValue(STM.getMaxPrivateElementSize(true)));
1601 if (STM.isXNACKEnabled())
1605 Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);