Lines Matching defs:ProgInfo
935 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
962 ProgInfo.NumArchVGPR = GetSymRefExpr(RIK::RIK_NumVGPR);
963 ProgInfo.NumAccVGPR = GetSymRefExpr(RIK::RIK_NumAGPR);
964 ProgInfo.NumVGPR = AMDGPUMCExpr::createTotalNumVGPR(
965 ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx);
967 ProgInfo.AccumOffset = computeAccumOffset(ProgInfo.NumArchVGPR, Ctx);
968 ProgInfo.TgSplit = STM.isTgSplitEnabled();
969 ProgInfo.NumSGPR = GetSymRefExpr(RIK::RIK_NumSGPR);
970 ProgInfo.ScratchSize = GetSymRefExpr(RIK::RIK_PrivateSegSize);
971 ProgInfo.VCCUsed = GetSymRefExpr(RIK::RIK_UsesVCC);
972 ProgInfo.FlatUsed = GetSymRefExpr(RIK::RIK_UsesFlatScratch);
973 ProgInfo.DynamicCallStack =
983 ProgInfo.VCCUsed, ProgInfo.FlatUsed,
991 if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) &&
999 ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs - 1);
1004 ProgInfo.NumSGPR = MCBinaryExpr::createAdd(ProgInfo.NumSGPR, ExtraSGPRs, Ctx);
1075 ProgInfo.NumSGPR = AMDGPUMCExpr::createMax(
1076 {ProgInfo.NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx);
1078 ProgInfo.NumArchVGPR = AMDGPUMCExpr::createMax(
1079 {ProgInfo.NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx);
1081 ProgInfo.NumVGPR = AMDGPUMCExpr::createTotalNumVGPR(
1082 ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx);
1090 ProgInfo.NumSGPR =
1091 AMDGPUMCExpr::createMax({ProgInfo.NumSGPR, UserPlusExtraSGPRs}, Ctx);
1097 ProgInfo.NumSGPRsForWavesPerEU =
1098 AMDGPUMCExpr::createMax({ProgInfo.NumSGPR, CreateExpr(1ul),
1101 ProgInfo.NumVGPRsForWavesPerEU =
1102 AMDGPUMCExpr::createMax({ProgInfo.NumVGPR, CreateExpr(1ul),
1110 if (TryGetMCExprValue(ProgInfo.NumSGPR, NumSgpr) &&
1119 ProgInfo.NumSGPR = CreateExpr(MaxAddressableNumSGPRs);
1120 ProgInfo.NumSGPRsForWavesPerEU = CreateExpr(MaxAddressableNumSGPRs);
1125 ProgInfo.NumSGPR =
1127 ProgInfo.NumSGPRsForWavesPerEU =
1162 ProgInfo.SGPRBlocks = GetNumGPRBlocks(ProgInfo.NumSGPRsForWavesPerEU,
1164 ProgInfo.VGPRBlocks = GetNumGPRBlocks(ProgInfo.NumVGPRsForWavesPerEU,
1171 ProgInfo.FloatMode = getFPMode(Mode);
1173 ProgInfo.IEEEMode = Mode.IEEE;
1176 ProgInfo.DX10Clamp = Mode.DX10Clamp;
1191 ProgInfo.SGPRSpill = MFI->getNumSpilledSGPRs();
1192 ProgInfo.VGPRSpill = MFI->getNumSpilledVGPRs();
1194 ProgInfo.LDSSize = MFI->getLDSSize();
1195 ProgInfo.LDSBlocks =
1196 alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1209 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
1211 ProgInfo.ScratchBlocks = DivideCeil(
1212 MCBinaryExpr::createMul(ProgInfo.ScratchSize,
1217 ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1218 ProgInfo.MemOrdered = 1;
1233 ProgInfo.ScratchEnable = MCBinaryExpr::createLOr(
1234 MCBinaryExpr::createGT(ProgInfo.ScratchBlocks,
1236 ProgInfo.DynamicCallStack, Ctx);
1238 ProgInfo.UserSGPR = MFI->getNumUserSGPRs();
1240 ProgInfo.TrapHandlerEnable =
1242 ProgInfo.TGIdXEnable = MFI->hasWorkGroupIDX();
1243 ProgInfo.TGIdYEnable = MFI->hasWorkGroupIDY();
1244 ProgInfo.TGIdZEnable = MFI->hasWorkGroupIDZ();
1245 ProgInfo.TGSizeEnable = MFI->hasWorkGroupInfo();
1246 ProgInfo.TIdIGCompCount = TIDIGCompCnt;
1247 ProgInfo.EXCPEnMSB = 0;
1249 ProgInfo.LdsSize = STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks;
1250 ProgInfo.EXCPEnable = 0;
1264 ProgInfo.ComputePGMRSrc3GFX90A =
1265 SetBits(ProgInfo.ComputePGMRSrc3GFX90A, ProgInfo.AccumOffset,
1268 ProgInfo.ComputePGMRSrc3GFX90A =
1269 SetBits(ProgInfo.ComputePGMRSrc3GFX90A, CreateExpr(ProgInfo.TgSplit),
1274 ProgInfo.Occupancy = AMDGPUMCExpr::createOccupancy(
1275 STM.computeOccupancy(F, ProgInfo.LDSSize).second,
1276 ProgInfo.NumSGPRsForWavesPerEU, ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);
1281 if (TryGetMCExprValue(ProgInfo.Occupancy, Occupancy) && Occupancy < MinWEU) {