Lines Matching defs:MI
52 uint64_t getBinaryCodeForInstr(const MCInst &MI,
58 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
66 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
72 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
78 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
84 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 uint32_t getCondCompBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
102 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
127 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
132 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
138 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
144 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
148 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
151 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
154 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
157 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
160 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
163 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
166 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
169 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
173 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
176 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
180 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
183 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
187 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
191 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
194 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
198 uint32_t EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
201 uint32_t EncodeZK(const MCInst &MI, unsigned OpIdx,
204 uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
208 uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
211 uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
215 uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,
219 uint32_t encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
229 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
240 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
243 const MCOperand &MO = MI.getOperand(OpIdx);
251 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
261 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
264 const MCOperand &MO = MI.getOperand(OpIdx);
272 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
275 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
287 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
291 const MCOperand &MO = MI.getOperand(OpIdx);
292 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
305 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
324 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
326 const MCOperand &MO = MI.getOperand(OpIdx);
334 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
345 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
347 const MCOperand &MO = MI.getOperand(OpIdx);
355 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
366 AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
369 const MCOperand &MO = MI.getOperand(OpIdx);
378 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
389 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
392 const MCOperand &MO = MI.getOperand(OpIdx);
400 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
409 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
412 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
413 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
418 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
421 const MCOperand &MO = MI.getOperand(OpIdx);
428 0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
438 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
440 const MCOperand &MO = MI.getOperand(OpIdx);
448 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
459 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
462 const MCOperand &MO = MI.getOperand(OpIdx);
469 MCFixupKind Kind = MI.getOpcode() == AArch64::BL
472 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
487 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
490 const MCOperand &MO = MI.getOperand(OpIdx);
512 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
514 const MCOperand &MO = MI.getOperand(OpIdx);
520 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
523 const MCOperand &MO = MI.getOperand(OpIdx);
529 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
532 const MCOperand &MO = MI.getOperand(OpIdx);
538 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
541 const MCOperand &MO = MI.getOperand(OpIdx);
547 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
550 const MCOperand &MO = MI.getOperand(OpIdx);
556 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
559 const MCOperand &MO = MI.getOperand(OpIdx);
565 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
568 const MCOperand &MO = MI.getOperand(OpIdx);
574 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
577 const MCOperand &MO = MI.getOperand(OpIdx);
583 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
586 const MCOperand &MO = MI.getOperand(OpIdx);
593 AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
597 auto RegOpnd = MI.getOperand(OpIdx).getReg();
606 uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,
609 auto RegOpnd = MI.getOperand(OpIdx).getReg();
623 AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
626 auto RegOpnd = MI.getOperand(OpIdx).getReg();
631 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
633 auto RegOpnd = MI.getOperand(OpIdx).getReg();
641 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
643 auto RegOpnd = MI.getOperand(OpIdx).getReg();
651 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
653 unsigned RegMask = MI.getOperand(OpIdx).getImm();
660 AArch64MCCodeEmitter::encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
663 auto RegOpnd = MI.getOperand(OpIdx).getReg();
668 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
672 auto ShiftOpnd = MI.getOperand(OpIdx + 1).getImm();
681 auto Immediate = MI.getOperand(OpIdx).getImm();
686 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
689 const MCOperand &MO = MI.getOperand(OpIdx);
698 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
700 const MCOperand &MO = MI.getOperand(OpIdx);
708 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
714 MCOperand UImm16MO = MI.getOperand(1);
740 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI,
745 if (MI.getOpcode() == AArch64::TLSDESCCALL) {
753 MCFixup::create(0, MI.getOperand(0).getExpr(),
758 if (MI.getOpcode() == AArch64::SPACE) {
763 uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
769 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
779 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
789 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {