Lines Matching defs:STI
75 StringRef Annot, const MCSubtargetInfo &STI,
82 if (printSysAlias(MI, STI, O)) {
88 if (printSyspAlias(MI, STI, O)) {
95 if (printRangePrefetchAlias(MI, STI, O, Annot))
218 (ImmR == 0 || ImmS < ImmR) && STI.hasFeature(AArch64::HasV8_2aOps)) {
375 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
376 printInstruction(MI, Address, STI, O);
785 const MCSubtargetInfo &STI,
797 printVectorList(MI, ListOpNum, STI, O, "");
811 printVectorList(MI, OpNum++, STI, O, "");
839 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
847 const MCSubtargetInfo &STI,
888 printOperand(MI, 1, STI, O); // "Rn".
897 const MCSubtargetInfo &STI,
941 if (!(STI.hasFeature(AArch64::FeatureAll) || STI.hasFeature(Requires)))
959 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
971 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
982 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
994 if (AT && AT->haveFeatures(STI.getFeatureBits())) {
998 } else if (DC && DC->haveFeatures(STI.getFeatureBits())) {
1010 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1033 const MCSubtargetInfo &STI,
1063 if (!STI.hasFeature(AArch64::FeatureXS))
1069 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1085 printSyspXzrPair(MI, 4, STI, O);
1087 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1094 const MCSubtargetInfo &STI,
1125 const MCSubtargetInfo &STI,
1138 const MCSubtargetInfo &STI,
1146 const MCSubtargetInfo &STI,
1157 const MCSubtargetInfo &STI,
1163 printImm(MI, OpNo, STI, O);
1171 const MCSubtargetInfo &STI,
1178 const MCSubtargetInfo &STI,
1186 const MCSubtargetInfo &STI,
1211 const MCSubtargetInfo &STI,
1219 const MCSubtargetInfo &STI,
1227 const MCSubtargetInfo &STI,
1237 printShifter(MI, OpNum + 1, STI, O);
1244 printShifter(MI, OpNum + 1, STI, O);
1250 const MCSubtargetInfo &STI,
1259 const MCSubtargetInfo &STI,
1272 const MCSubtargetInfo &STI,
1275 printShifter(MI, OpNum + 1, STI, O);
1279 const MCSubtargetInfo &STI,
1282 printArithExtend(MI, OpNum + 1, STI, O);
1286 const MCSubtargetInfo &STI,
1343 const MCSubtargetInfo &STI,
1345 printOperand(MI, OpNum, STI, O);
1361 const MCSubtargetInfo &STI,
1389 const MCSubtargetInfo &STI,
1396 const MCSubtargetInfo &STI,
1403 const MCSubtargetInfo &STI,
1412 const MCSubtargetInfo &STI,
1420 const MCSubtargetInfo &STI,
1455 const MCSubtargetInfo &STI,
1468 const MCSubtargetInfo &STI,
1478 if (PRFM && PRFM->haveFeatures(STI.getFeatureBits())) {
1488 const MCSubtargetInfo &STI,
1499 const MCSubtargetInfo &STI,
1510 const MCSubtargetInfo &STI,
1620 const MCSubtargetInfo &STI,
1637 const MCSubtargetInfo &STI,
1662 const MCSubtargetInfo &STI,
1747 const MCSubtargetInfo &STI,
1749 printVectorList(MI, OpNum, STI, O, "");
1754 const MCSubtargetInfo &STI,
1757 printVectorList(MI, OpNum, STI, O, "");
1766 printVectorList(MI, OpNum, STI, O, Suffix);
1771 const MCSubtargetInfo &STI,
1778 const MCSubtargetInfo &STI,
1785 const MCSubtargetInfo &STI,
1814 const MCSubtargetInfo &STI,
1839 const MCSubtargetInfo &STI,
1862 const MCSubtargetInfo &STI,
1878 const MCSubtargetInfo &STI) {
1880 Reg.haveFeatures(STI.getFeatureBits());
1888 const MCSubtargetInfo &STI) {
1891 if (isValidSysReg(Reg, Read, STI))
1899 const MCSubtargetInfo &STI,
1917 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI);
1926 const MCSubtargetInfo &STI,
1944 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI);
1953 const MCSubtargetInfo &STI,
1959 if (PStateImm15 && PStateImm15->haveFeatures(STI.getFeatureBits()))
1961 else if (PStateImm1 && PStateImm1->haveFeatures(STI.getFeatureBits()))
1968 const MCSubtargetInfo &STI,
1977 const MCSubtargetInfo &STI,
1984 const MCSubtargetInfo &STI,
1995 const MCSubtargetInfo &STI,
2010 const MCSubtargetInfo &STI,
2049 const MCSubtargetInfo &STI,
2059 printShifter(MI, OpNum + 1, STI, O);
2074 const MCSubtargetInfo &STI,
2093 const MCSubtargetInfo &STI,
2111 const MCSubtargetInfo &STI,
2121 const MCSubtargetInfo &STI,
2128 const MCSubtargetInfo &STI,
2135 const MCSubtargetInfo &STI,
2144 const MCSubtargetInfo &STI,