Lines Matching defs:MI
74 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
79 unsigned Opcode = MI->getOpcode();
82 if (printSysAlias(MI, STI, O)) {
88 if (printSyspAlias(MI, STI, O)) {
95 if (printRangePrefetchAlias(MI, STI, O, Annot))
102 const MCOperand &Op0 = MI->getOperand(0);
103 const MCOperand &Op1 = MI->getOperand(1);
104 const MCOperand &Op2 = MI->getOperand(2);
105 const MCOperand &Op3 = MI->getOperand(3);
212 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
213 const MCOperand &Op2 = MI->getOperand(2);
214 int ImmR = MI->getOperand(3).getImm();
215 int ImmS = MI->getOperand(4).getImm();
270 MI->getOperand(1).isExpr()) {
276 printRegName(O, MI->getOperand(0).getReg());
281 MI->getOperand(1).getExpr()->print(O, &MAI);
287 MI->getOperand(2).isExpr()) {
289 printRegName(O, MI->getOperand(0).getReg());
294 MI->getOperand(2).getExpr()->print(O, &MAI);
302 printRegName(O, MI->getOperand(0).getReg());
322 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
324 int Shift = MI->getOperand(2).getImm();
325 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
335 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
337 int Shift = MI->getOperand(2).getImm();
338 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
349 (MI->getOperand(1).getReg() == AArch64::XZR ||
350 MI->getOperand(1).getReg() == AArch64::WZR) &&
351 MI->getOperand(2).isImm()) {
354 MI->getOperand(2).getImm(), RegWidth);
363 << MI->getOperand(1).getImm();
375 if (!PrintAliases || !printAliasInstr(MI, Address, STI, O))
376 printInstruction(MI, Address, STI, O);
381 (MI->getOperand(0).getReg() == AArch64::XZR ||
382 MI->getOperand(0).getReg() == AArch64::WZR)) {
783 void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
787 unsigned Opcode = MI->getOpcode();
791 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
793 printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
797 printVectorList(MI, ListOpNum, STI, O, "");
800 printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
811 printVectorList(MI, OpNum++, STI, O, "");
814 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
817 MCRegister AddrReg = MI->getOperand(OpNum++).getReg();
824 MCRegister Reg = MI->getOperand(OpNum++).getReg();
839 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
846 bool AArch64InstPrinter::printRangePrefetchAlias(const MCInst *MI,
850 unsigned Opcode = MI->getOpcode();
857 unsigned PRFOp = MI->getOperand(0).getImm();
862 MCRegister Rm = MI->getOperand(2).getReg();
869 unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
870 unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
888 printOperand(MI, 1, STI, O); // "Rn".
896 bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
900 unsigned Opcode = MI->getOpcode();
904 const MCOperand &Op1 = MI->getOperand(0);
905 const MCOperand &Cn = MI->getOperand(1);
906 const MCOperand &Cm = MI->getOperand(2);
907 const MCOperand &Op2 = MI->getOperand(3);
1026 printRegName(O, MI->getOperand(4).getReg());
1032 bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
1036 unsigned Opcode = MI->getOpcode();
1041 const MCOperand &Op1 = MI->getOperand(0);
1042 const MCOperand &Cn = MI->getOperand(1);
1043 const MCOperand &Cm = MI->getOperand(2);
1044 const MCOperand &Op2 = MI->getOperand(3);
1084 if (MI->getOperand(4).getReg() == AArch64::XZR)
1085 printSyspXzrPair(MI, 4, STI, O);
1087 printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
1093 void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
1096 const MCOperand &RegOp = MI->getOperand(OpNum);
1124 void AArch64InstPrinter::printMatrixTileVector(const MCInst *MI, unsigned OpNum,
1127 const MCOperand &RegOp = MI->getOperand(OpNum);
1137 void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
1140 const MCOperand &RegOp = MI->getOperand(OpNum);
1145 void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
1148 const MCOperand &MO = MI->getOperand(OpNum);
1156 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
1159 const MCOperand &Op = MI->getOperand(OpNo);
1163 printImm(MI, OpNo, STI, O);
1170 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
1173 const MCOperand &Op = MI->getOperand(OpNo);
1177 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
1180 const MCOperand &Op = MI->getOperand(OpNo);
1185 void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
1188 const MCOperand &Op = MI->getOperand(OpNo);
1197 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
1199 const MCOperand &Op = MI->getOperand(OpNo);
1210 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1213 const MCOperand &Op = MI->getOperand(OpNo);
1218 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1221 const MCOperand &Op = MI->getOperand(OpNo);
1226 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1229 const MCOperand &MO = MI->getOperand(OpNum);
1234 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1237 printShifter(MI, OpNum + 1, STI, O);
1244 printShifter(MI, OpNum + 1, STI, O);
1249 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
1252 uint64_t Val = MI->getOperand(OpNum).getImm();
1258 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1261 unsigned Val = MI->getOperand(OpNum).getImm();
1271 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1274 printRegName(O, MI->getOperand(OpNum).getReg());
1275 printShifter(MI, OpNum + 1, STI, O);
1278 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1281 printRegName(O, MI->getOperand(OpNum).getReg());
1282 printArithExtend(MI, OpNum + 1, STI, O);
1285 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1288 unsigned Val = MI->getOperand(OpNum).getImm();
1296 MCRegister Dest = MI->getOperand(0).getReg();
1297 MCRegister Src1 = MI->getOperand(1).getReg();
1332 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1335 bool SignExtend = MI->getOperand(OpNum).getImm();
1336 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1341 void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1345 printOperand(MI, OpNum, STI, O);
1359 void AArch64InstPrinter::printPredicateAsCounter(const MCInst *MI,
1363 MCRegister Reg = MI->getOperand(OpNum).getReg();
1388 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1391 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1395 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1398 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1402 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1406 printRegName(O, MI->getOperand(OpNum).getReg());
1411 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1415 << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1419 void AArch64InstPrinter::printImmRangeScale(const MCInst *MI, unsigned OpNum,
1422 unsigned FirstImm = Scale * MI->getOperand(OpNum).getImm();
1427 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1429 const MCOperand MO = MI->getOperand(OpNum);
1438 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1440 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1442 printRegName(O, MI->getOperand(OpNum).getReg());
1454 void AArch64InstPrinter::printRPRFMOperand(const MCInst *MI, unsigned OpNum,
1457 unsigned prfop = MI->getOperand(OpNum).getImm();
1467 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1470 unsigned prfop = MI->getOperand(OpNum).getImm();
1487 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1490 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1498 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1501 unsigned btihintop = MI->getOperand(OpNum).getImm() ^ 32;
1509 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1512 const MCOperand &MO = MI->getOperand(OpNum);
1618 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1624 MCRegister Reg = MI->getOperand(OpNum).getReg();
1636 void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
1640 unsigned RegMask = MI->getOperand(OpNum).getImm();
1661 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1665 MCRegister Reg = MI->getOperand(OpNum).getReg();
1745 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1749 printVectorList(MI, OpNum, STI, O, "");
1753 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1757 printVectorList(MI, OpNum, STI, O, "");
1766 printVectorList(MI, OpNum, STI, O, Suffix);
1770 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1773 O << "[" << Scale * MI->getOperand(OpNum).getImm() << "]";
1777 void AArch64InstPrinter::printMatrixIndex(const MCInst *MI, unsigned OpNum,
1780 O << Scale * MI->getOperand(OpNum).getImm();
1783 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1787 const MCOperand &Op = MI->getOperand(OpNum);
1802 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1808 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1812 void AArch64InstPrinter::printAdrAdrpLabel(const MCInst *MI, uint64_t Address,
1816 const MCOperand &Op = MI->getOperand(OpNum);
1822 if (MI->getOpcode() == AArch64::ADRP) {
1835 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1838 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1841 unsigned Val = MI->getOperand(OpNo).getImm();
1842 unsigned Opcode = MI->getOpcode();
1861 void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1864 unsigned Val = MI->getOperand(OpNo).getImm();
1865 assert(MI->getOpcode() == AArch64::DSBnXS);
1898 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1901 unsigned Val = MI->getOperand(OpNo).getImm();
1925 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1928 unsigned Val = MI->getOperand(OpNo).getImm();
1952 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1955 unsigned Val = MI->getOperand(OpNo).getImm();
1967 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1970 unsigned RawVal = MI->getOperand(OpNo).getImm();
1976 void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1979 unsigned Val = MI->getOperand(OpNo).getImm();
1983 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1986 unsigned Val = MI->getOperand(OpNum).getImm();
1993 void AArch64InstPrinter::printSVEVecLenSpecifier(const MCInst *MI,
1997 unsigned Val = MI->getOperand(OpNum).getImm();
2009 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
2023 MCRegister Reg = MI->getOperand(OpNum).getReg();
2048 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
2051 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
2052 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
2059 printShifter(MI, OpNum + 1, STI, O);
2073 void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
2079 uint64_t Val = MI->getOperand(OpNum).getImm();
2092 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
2105 MCRegister Reg = MI->getOperand(OpNum).getReg();
2110 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
2115 unsigned Val = MI->getOperand(OpNum).getImm();
2120 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
2123 MCRegister Reg = MI->getOperand(OpNum).getReg();
2127 void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
2130 MCRegister Reg = MI->getOperand(OpNum).getReg();
2134 void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
2137 MCRegister Reg = MI->getOperand(OpNum).getReg();
2143 void AArch64InstPrinter::printPHintOp(const MCInst *MI, unsigned OpNum,
2146 unsigned Op = MI->getOperand(OpNum).getImm();