Lines Matching defs:OpcTable
1618 static const unsigned OpcTable[2][2] = {{AArch64::TBZX, AArch64::TBNZX},
1620 unsigned Opc = OpcTable[UseWReg][IsNegative];
1681 static const unsigned OpcTable[2][2] = {{AArch64::CBZW, AArch64::CBZX},
1683 unsigned Opc = OpcTable[IsNegative][Width == 64];
2652 static const unsigned OpcTable[2][2] = {
2657 unsigned Opc = OpcTable[IsSigned][Size == 64];
4429 const std::array<std::array<unsigned, 2>, 5> OpcTable{
4435 return emitAddSub(OpcTable, DefReg, LHS, RHS, MIRBuilder);
4442 const std::array<std::array<unsigned, 2>, 5> OpcTable{
4448 return emitAddSub(OpcTable, Dst, LHS, RHS, MIRBuilder);
4455 const std::array<std::array<unsigned, 2>, 5> OpcTable{
4461 return emitAddSub(OpcTable, Dst, LHS, RHS, MIRBuilder);
4471 static const unsigned OpcTable[2] = {AArch64::ADCSXr, AArch64::ADCSWr};
4472 return emitInstr(OpcTable[Is32Bit], {Dst}, {LHS, RHS}, MIRBuilder);
4482 static const unsigned OpcTable[2] = {AArch64::SBCSXr, AArch64::SBCSWr};
4483 return emitInstr(OpcTable[Is32Bit], {Dst}, {LHS, RHS}, MIRBuilder);
4503 const unsigned OpcTable[3][2] = {{AArch64::ANDSXri, AArch64::ANDSWri},
4512 auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS});
4520 return emitInstr(OpcTable[1][Is32Bit], {Ty}, {LHS}, MIRBuilder, Fns);
4521 return emitInstr(OpcTable[2][Is32Bit], {Ty}, {LHS, RHS}, MIRBuilder);
4686 static const unsigned OpcTable[2] = {AArch64::CSINCWr, AArch64::CSINCXr};
4687 unsigned Opc = OpcTable[Size == 64];