Lines Matching defs:CondCode

317                            AArch64CC::CondCode CC,
324                           AArch64CC::CondCode Pred,
341   std::pair<MachineInstr *, AArch64CC::CondCode>
349   MachineInstr *emitConjunction(Register Val, AArch64CC::CondCode &OutCC,
353                                           AArch64CC::CondCode Predicate,
354                                           AArch64CC::CondCode OutCC,
356   MachineInstr *emitConjunctionRec(Register Val, AArch64CC::CondCode &OutCC,
358                                    AArch64CC::CondCode Predicate,
1182                                        Register False, AArch64CC::CondCode CC,
1351 static AArch64CC::CondCode changeICMPPredToAArch64CC(CmpInst::Predicate P) {
1380                                     AArch64CC::CondCode &CondCode,
1381                                     AArch64CC::CondCode &CondCode2) {
1387     CondCode = AArch64CC::EQ;
1390     CondCode = AArch64CC::GT;
1393     CondCode = AArch64CC::GE;
1396     CondCode = AArch64CC::MI;
1399     CondCode = AArch64CC::LS;
1402     CondCode = AArch64CC::MI;
1406     CondCode = AArch64CC::VC;
1409     CondCode = AArch64CC::VS;
1412     CondCode = AArch64CC::EQ;
1416     CondCode = AArch64CC::HI;
1419     CondCode = AArch64CC::PL;
1422     CondCode = AArch64CC::LT;
1425     CondCode = AArch64CC::LE;
1428     CondCode = AArch64CC::NE;
1437                                      AArch64CC::CondCode &CondCode,
1438                                      AArch64CC::CondCode &CondCode2) {
1442     changeFPCCToORAArch64CC(CC, CondCode, CondCode2);
1449     CondCode = AArch64CC::VC;
1456     CondCode = AArch64CC::PL;
1698   AArch64CC::CondCode CC1, CC2;
1814   const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
2503     const AArch64CC::CondCode InvCC =
3568     const AArch64CC::CondCode InvCC =
4551   AArch64CC::CondCode CC1, CC2;
4673                                       Register Src2, AArch64CC::CondCode Pred,
4765 std::pair<MachineInstr *, AArch64CC::CondCode>
4861     AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC,
4894   AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
4910     Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp,
4911     AArch64CC::CondCode Predicate, MachineIRBuilder &MIB) const {
4926       AArch64CC::CondCode ExtraCC;
5011   AArch64CC::CondCode RHSCC;
5024     Register Val, AArch64CC::CondCode &OutCC, MachineIRBuilder &MIB) const {
5035   AArch64CC::CondCode AArch64CC;
5087   AArch64CC::CondCode CondCode;
5091     CondCode = changeICMPPredToAArch64CC(Pred);
5098     AArch64CC::CondCode CondCode2;
5099     changeFCMPPredToAArch64CC(Pred, CondCode, CondCode2);
5117              I.getOperand(3).getReg(), CondCode, MIB);