Lines Matching defs:Rm
654 unsigned Rm = fieldFromInstruction(insn, 16, 5);
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
708 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1330 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1346 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1355 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1364 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1373 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1382 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1391 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1792 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1797 if (Rd == Rm || Rm == Rn || Rd == Rn)
1800 // Rd and Rn (not Rm) register operands are written back, so they appear
1811 Inst, Rm, Addr, Decoder))
1830 uint64_t Rm = fieldFromInstruction(insn, 16, 5);
1840 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1844 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,