Lines Matching refs:cycle

288 // b.	Link Register Update on pipes 0 and 1 taking 1 cycle
289 // c.	Indirect branch on pipe 0 taking 1 cycle
301 // 1 cycle on I012345
304 // 1 cycle on I0123
307 // 1 cycle on 2 of I012345
311 // 2 cycle on 2 of I0123 with ReleaseAtCycles
318 // 2 cycle on 2 of I012345
325 // 3 cycle on 2 of I45
332 // 3 cycle on I45
337 // 7 cycle on I2 32-bit integer division
343 // 9 cycle on I2 64-bit integer division
351 // 4 cycle on LS(P6789)
356 // 4 cycle for Post/Pre inc/dec access, also covers all pair loads Post/Pre
402 // 6 cycle for Post/Pre inc/dec access
442 // 1 cycle for all generic stores
473 // 1 cycle for neon write: float + ASIMD with Post/Pre Inc/Dec access
525 // Latency is 3, FCVT is also 3 cycle
576 // 2 cycle on FP1
581 // 3 cycle on FP1
586 // 4 cycle , 0.5 throughput on FP1
592 // 5 cycle , 1 throughput on FP1
597 // 8 cycle , 2 throughput on FP0123
728 // 3 uOp, 1 cycle for branch, 7 cycle for Authentication,
729 // 1 cycle for updating link register
864 // 4 cycle Load-to-use from L1D$
865 // Neon load with 5 cycle
866 // 6 cycle to STA ?
867 // STD cycle ?
1093 // ASIMD Load instructions, 4 cycle access + 2 cycle NEON access
1397 // floating unary, cycle/throughput? xls row14