Lines Matching defs:MOP

942     bool isDef = any_of(I.operands(), [DefReg, TRI](MachineOperand &MOP) {
943       return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
944              TRI->regsOverlap(MOP.getReg(), DefReg);
957   for (const MachineOperand &MOP : phys_regs_and_masks(MI))
958     if (MOP.isReg() && MOP.isKill())
959       Units.removeReg(MOP.getReg());
961   for (const MachineOperand &MOP : phys_regs_and_masks(MI))
962     if (MOP.isReg() && !MOP.isKill())
963       Units.addReg(MOP.getReg());
1010               MachineOperand &MOP = MI.getOperand(OpIdx);
1013               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
1015                    (MOP.isDef() && MOP.isImplicit())) &&
1016                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
1017                 assert((MOP.isImplicit() ||
1018                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
1028                       TRI->getMinimalPhysRegClass(MOP.getReg()));
1030                 MOP.setReg(MatchingReg);
1036               MachineOperand &MOP = MI.getOperand(OpIdx);
1037               if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
1038                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
1039                 assert((MOP.isImplicit() ||
1040                         (MOP.isRenamable() && !MOP.isEarlyClobber())) &&
1048                       TRI->getMinimalPhysRegClass(MOP.getReg()));
1051                 MOP.setReg(MatchingReg);
1078                     [this, RegToCheck](const MachineOperand &MOP) {
1079                       return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
1080                              MOP.isUndef() ||
1081                              !TRI->regsOverlap(MOP.getReg(), RegToCheck);
1236     for (const MachineOperand &MOP : phys_regs_and_masks(*I))
1237       if (MOP.isReg() && MOP.isKill())
1238         DefinedInBB.addReg(MOP.getReg());
1542 static bool canRenameMOP(const MachineOperand &MOP,
1544   if (MOP.isReg()) {
1545     auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());
1559           << MOP << ")\n");
1566     if (MOP.isImplicit() && MOP.isDef()) {
1567       if (!isRewritableImplicitDef(MOP.getParent()->getOpcode()))
1570           MOP.getParent()->getOperand(0).getReg(), MOP.getReg());
1573   return MOP.isImplicit() ||
1574          (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
1591               [TRI, RegToRename](const MachineOperand &MOP) {
1592                 return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
1593                        MOP.isImplicit() && MOP.isKill() &&
1594                        TRI->regsOverlap(RegToRename, MOP.getReg());
1636       for (auto &MOP : MI.operands()) {
1637         if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||
1638             !TRI->regsOverlap(MOP.getReg(), RegToRename))
1640         if (!canRenameMOP(MOP, TRI)) {
1641           LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);
1644         RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
1648       for (auto &MOP : MI.operands()) {
1649         if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
1650             !TRI->regsOverlap(MOP.getReg(), RegToRename))
1653         if (!canRenameMOP(MOP, TRI)) {
1654           LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);
1657         RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));
1703         for (auto &MOP : MI.operands()) {
1704           if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
1705               !TRI->regsOverlap(MOP.getReg(), RegToRename))
1707           if (!canRenameMOP(MOP, TRI)) {
1708             LLVM_DEBUG(dbgs() << "  Cannot rename " << MOP << " in " << MI);
1711           RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg()));