Lines Matching +refs:tablegen +refs:mode +refs:syntax +refs:table

1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
245 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
298 // A subset of NEON instructions are legal in Streaming SVE execution mode,
303 // A subset of NEON instructions are legal in Streaming SVE mode only with +sme2p2.
1211 // 32-bit jump table destination is actually only 2 instructions since we can
1212 // use the table itself as a PC-relative base. But optimization occurs after
1217                              (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
1220                              (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
1223                             (ins GPR64:$table, GPR64:$entry, i32imm:$jti), []>,
1227 // A hardened but more expensive version of jump-table dispatch.
1235 // jump-table array.  When it doesn't, this branches to the first entry.
1239 // to avoid signing jump-table entries and turning them into pointers.
1251   let Size = 44; // 28 fixed + 16 variable, for table size materialization
2234 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
3881 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
4152 // FIXME: Use dedicated range-checked addressing mode operand here.
9084 // In big endian mode every memory access has an implicit byte swap. LDR and
10268     // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)
10303 // Instruction syntax: