Lines Matching defs:Pg
4592 SDValue Pg = getPredicateForVector(DAG, DL, MVT::nxv2f32);
4594 Pg, SrcVal, DAG.getUNDEF(MVT::nxv2f32));
15479 SDValue Pg = getPredicateForScalableVector(DAG, dl, VT);
15481 DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, VT, Pg, Op->getOperand(0),
19678 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
19724 SDValue Pg = getPTrue(DAG, SDLoc(N), VT, AArch64SVEPredPattern::all);
19725 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::FIRST_ACTIVE);
19761 SDValue Pg = getPTrue(DAG, SDLoc(N), OpVT, AArch64SVEPredPattern::all);
19762 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE);
21651 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
21659 assert(Op.getValueType() == Pg.getValueType() &&
21671 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Pg);
21673 Pg = getSVEPredicateBitCast(MVT::nxv16i1, Pg, DAG);
21680 DL, MVT::i32, Pg, Op);
21756 SDValue Pg = N->getOperand(1);
21761 if (isAllActivePredicate(DAG, Pg)) {
21765 return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg, Op1, Op2);
22587 N->getOperand(2), // Pg
22666 N->getOperand(3), // Pg
23250 SDValue Pg = N->getOperand(1);
23272 if (ExtPg == Pg && ExtFromEVT == MVT::i32) {
23280 {Chain, Pg, Base, UnextendedOffset, Ty});
25696 N->getOperand(3), // Pg
25793 N->getOperand(2), // Pg
28446 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
28454 LoadVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(), Pg,
28465 Pg, Result, DAG.getUNDEF(ContainerVT));
28481 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
28484 return Pg;
28489 return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, Pg.getValueType(),
28490 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)});
28554 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
28561 NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg,
28573 Store->getBasePtr(), Store->getOffset(), Pg, MemVT,
28611 SDValue Pg = getPredicateForFixedLengthVector(DAG, dl, VT);
28613 DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, ContainerVT, Pg, Op1, Op2);
28770 auto Pg = getPredicateForVector(DAG, DL, VT);
28777 SmallVector<SDValue, 4> Operands = {Pg};
28805 SmallVector<SDValue, 4> Operands = {Pg};
28865 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
28874 Pg, AccOp, VecOp);
28889 SDValue Pg = getPredicateForVector(DAG, DL, OpVT);
28895 if (isAllActivePredicate(DAG, Pg) && OpVT == MVT::nxv16i1)
28900 return getPTest(DAG, VT, Pg, Op, AArch64CC::ANY_ACTIVE);
28902 Op = DAG.getNode(ISD::XOR, DL, OpVT, Op, Pg);
28903 return getPTest(DAG, VT, Pg, Op, AArch64CC::NONE_ACTIVE);
28910 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Pg);
28914 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64, ID, Pg, Op);
28957 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT);
28958 SDValue Rdx = DAG.getNode(Opcode, DL, RdxVT, Pg, VecOp);
29007 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
29009 EVT CmpVT = Pg.getValueType();
29011 {Pg, Op1, Op2, Op.getOperand(2)});
29058 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
29062 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2);
29075 SDValue Pg = getPredicateForVector(DAG, DL, VT);
29087 Pg, Val, DAG.getUNDEF(ContainerVT));
29104 SDValue Pg = getPredicateForVector(DAG, DL, RoundVT);
29107 Val = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, RoundVT, Pg, Val,
29133 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
29142 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
29148 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
29151 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));
29272 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, VT);
29279 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val,
29284 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT);
29289 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT));