Lines Matching defs:IntermediateVT

29924     LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
29927       Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
29933   assert(IntermediateVT == RegisterVT && "Unexpected VT mismatch!");
29944     IntermediateVT = NewVT;
29961     IntermediateVT = RegisterVT = MVT::v16i8;
29964     IntermediateVT = RegisterVT = MVT::v8i16;
29967     IntermediateVT = RegisterVT = MVT::v4i32;
29970     IntermediateVT = RegisterVT = MVT::v2i64;
29973     IntermediateVT = RegisterVT = MVT::v8f16;
29976     IntermediateVT = RegisterVT = MVT::v4f32;
29979     IntermediateVT = RegisterVT = MVT::v2f64;
29982     IntermediateVT = RegisterVT = MVT::v8bf16;