Lines Matching defs:CSEL
2423 case AArch64ISD::CSEL: {
2675 MAKE_CASE(AArch64ISD::CSEL)
4277 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
4327 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
4357 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);
4367 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);
4417 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
7150 // Generate SUBS and CSEL for integer abs.
7160 // Generate SUBS & CSEL.
7164 return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,
11062 SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
11070 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
11089 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
11093 // this case, we emit the first CSEL and then emit a second using the output
11099 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
11102 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
11133 return DAG.getNode(AArch64ISD::CSEL, DL, OpVT, FVal, TVal, CCVal,
11200 unsigned Opcode = AArch64ISD::CSEL;
11214 // with a CSINV rather than a CSEL.
11222 // that we can match with a CSNEG rather than a CSEL.
11235 // instead of a CSEL in that case.
11278 if (Opcode != AArch64ISD::CSEL) {
11287 // is one, zero or negative one in the case of a CSEL. We can always
11288 // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
11291 if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
11348 // Emit first, and possibly only, CSEL.
11350 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
11352 // If we need a second CSEL, emit it, using the output of the first as the
11356 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
11359 // Otherwise, return the output of the first CSEL.
11458 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
19296 if (CSel0.getOpcode() != AArch64ISD::CSEL ||
19297 CSel1.getOpcode() != AArch64ISD::CSEL)
19354 return DAG.getNode(AArch64ISD::CSEL, DL, VT, CSel0.getOperand(0),
20321 if (Op.getOpcode() != AArch64ISD::CSEL)
20407 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
20448 /// CSEL(c, 1, cc) + b => CSINC(b+c, b, cc)
20459 if (LHS.getOpcode() != AArch64ISD::CSEL &&
20462 if (LHS.getOpcode() != AArch64ISD::CSEL &&
20474 // The CSEL should include a const one operand, and the CSNEG should include
20481 if (!(LHS.getOpcode() == AArch64ISD::CSEL &&
20487 // Switch CSEL(1, c, cc) to CSEL(c, 1, !cc)
20488 if (LHS.getOpcode() == AArch64ISD::CSEL && CTVal->isOne() &&
20511 assert(((LHS.getOpcode() == AArch64ISD::CSEL && CFVal->isOne()) ||
20568 if (CSel.getOpcode() != AArch64ISD::CSEL || !CSel->hasOneUse())
20584 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0N, N1N, CSel.getOperand(2),
20646 // (CSEL 1 0 CC Cond) => CC
20647 // (CSEL 0 1 CC Cond) => !CC
20649 if (Op.getOpcode() != AArch64ISD::CSEL)
21683 // NOTE: Cond is inverted to promote CSEL's removal when it feeds a compare.
21685 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);
24651 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) x)) => (CSEL l r cc2 cond)
24652 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) y)) => (CSEL l r !cc2 cond)
24655 // (CSEL l r NE (CMP (CSEL x y cc2 cond) x)) => (CSEL l r !cc2 cond)
24656 // (CSEL l r NE (CMP (CSEL x y cc2 cond) y)) => (CSEL l r cc2 cond)
24671 if (CmpRHS.getOpcode() == AArch64ISD::CSEL)
24673 else if (CmpLHS.getOpcode() != AArch64ISD::CSEL)
24708 return DAG.getNode(AArch64ISD::CSEL, DL, VT, L, R, CCValue, Cond);
24711 // Reassociate the true/false expressions of a CSEL instruction to obtain a
24713 // (CSEL (ADD (ADD x y) -c) f LO (SUBS x c)) to
24714 // (CSEL (ADD (SUBS x c) y) f LO (SUBS x c)) such that (SUBS x c) is a common
24782 return DAG.getNode(AArch64ISD::CSEL, SDLoc(N), VT, TValReassoc, FValReassoc,
24853 // Optimize CSEL instructions
24857 // CSEL x, x, cc -> x
24869 // CSEL 0, cttz(X), eq(X, 0) -> AND cttz bitwidth-1
24870 // CSEL cttz(X), 0, ne(X, 0) -> AND cttz bitwidth-1
24874 // CSEL a, b, cc, SUBS(x, y) -> CSEL a, b, swapped(cc), SUBS(y, x)
24891 return DAG.getNode(AArch64ISD::CSEL, DL, N->getVTList(), N->getOperand(0),
24980 LHS->getOpcode() == AArch64ISD::CSEL &&
24983 // Invert CSEL's condition.
24989 SDValue CSEL =
24990 DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),
24993 return DAG.getZExtOrTrunc(CSEL, DL, VT);
26489 case AArch64ISD::CSEL: