Lines Matching defs:AArch64TargetLowering
9 // This file implements the AArch64TargetLowering class.
151 // See [AArch64TargetLowering::fallbackToDAGISel] for implementation details.
376 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
1897 void AArch64TargetLowering::addTypeForNEON(MVT VT) {
2023 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
2043 bool AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(
2058 bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
2069 bool AArch64TargetLowering::shouldExpandVectorMatch(EVT VT,
2082 void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
2226 void AArch64TargetLowering::addDRType(MVT VT) {
2232 void AArch64TargetLowering::addQRType(MVT VT) {
2238 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &,
2361 bool AArch64TargetLowering::targetShrinkDemandedConstant(
2407 void AArch64TargetLowering::computeKnownBitsForTargetNode(
2535 unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode(
2572 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
2577 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
2615 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(
2641 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2646 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
2987 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
3046 MachineBasicBlock *AArch64TargetLowering::EmitLoweredCatchRet(
3055 AArch64TargetLowering::EmitDynamicProbedAlloc(MachineInstr &MI,
3071 AArch64TargetLowering::EmitTileLoad(unsigned Opc, unsigned BaseReg,
3089 AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const {
3104 MachineBasicBlock *AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
3121 AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
3155 AArch64TargetLowering::EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const {
3172 AArch64TargetLowering::EmitInitTPIDR2Object(MachineInstr &MI,
3202 AArch64TargetLowering::EmitAllocateZABuffer(MachineInstr &MI,
3247 AArch64TargetLowering::EmitAllocateSMESaveBuffer(MachineInstr &MI,
3278 AArch64TargetLowering::EmitGetSMESaveSize(MachineInstr &MI,
3303 MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
4250 SDValue AArch64TargetLowering::LowerXOR(SDValue Op, SelectionDAG &DAG) const {
4479 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
4560 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
4699 SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
4787 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
4820 AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
4924 SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
4981 SDValue AArch64TargetLowering::LowerVectorXRINT(SDValue Op,
5001 SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
5091 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
5232 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
5268 SDValue AArch64TargetLowering::LowerBITCAST(SDValue Op,
5410 SDValue AArch64TargetLowering::LowerGET_ROUNDING(SDValue Op,
5433 SDValue AArch64TargetLowering::LowerSET_ROUNDING(SDValue Op,
5477 SDValue AArch64TargetLowering::LowerGET_FPMODE(SDValue Op,
5496 SDValue AArch64TargetLowering::LowerSET_FPMODE(SDValue Op,
5511 SDValue AArch64TargetLowering::LowerRESET_FPMODE(SDValue Op,
5592 SDValue AArch64TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5768 SDValue AArch64TargetLowering::getRuntimePStateSM(SelectionDAG &DAG,
5936 SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
5978 SDValue AArch64TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
6011 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6545 bool AArch64TargetLowering::shouldExtendGSIndex(EVT VT, EVT &EltTy) const {
6554 bool AArch64TargetLowering::shouldRemoveExtendFromGSIndex(SDValue Extend,
6570 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
6645 SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
6744 SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,
6825 SDValue AArch64TargetLowering::LowerMLOAD(SDValue Op, SelectionDAG &DAG) const {
6886 SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
6964 SDValue AArch64TargetLowering::LowerStore128(SDValue Op,
6995 SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,
7052 SDValue AArch64TargetLowering::LowerVECTOR_COMPRESS(SDValue Op,
7151 SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
7253 SDValue AArch64TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
7263 SDValue AArch64TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
7310 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
7659 bool AArch64TargetLowering::mergeStoresAfterLegalization(EVT VT) const {
7663 bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
7727 bool AArch64TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,
7744 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
7807 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
7825 SDValue AArch64TargetLowering::LowerFormalArguments(
8300 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
8398 SDValue AArch64TargetLowering::LowerCallResult(
8496 static void analyzeCallOperands(const AArch64TargetLowering &TLI,
8547 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
8704 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
8735 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
8803 void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
8866 SDValue AArch64TargetLowering::changeStreamingMode(SelectionDAG &DAG, SDLoc DL,
8895 static SDValue emitSMEStateSaveRestore(const AArch64TargetLowering &TLI,
8937 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
9705 bool AArch64TargetLowering::CanLowerReturn(
9716 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
9866 SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
9873 SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
9879 SDValue AArch64TargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
9886 SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty,
9892 SDValue AArch64TargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
9900 SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG,
9902 LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getGOT\n");
9918 SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG,
9920 LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrLarge\n");
9934 SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
9936 LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddr\n");
9948 SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG,
9950 LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrTiny\n");
9957 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
10019 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
10085 SDValue AArch64TargetLowering::LowerELFTLSLocalExec(const GlobalValue *GV,
10191 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
10210 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
10299 AArch64TargetLowering::LowerWindowsGlobalTLSAddress(SDValue Op,
10357 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
10426 AArch64TargetLowering::LowerPtrAuthGlobalAddress(SDValue Op,
10515 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
10652 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
10745 SDValue AArch64TargetLowering::LowerCTPOP_PARITY(SDValue Op,
10844 SDValue AArch64TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10855 SDValue AArch64TargetLowering::LowerMinMax(SDValue Op,
10902 SDValue AArch64TargetLowering::LowerBitreverse(SDValue Op,
11016 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
11107 SDValue AArch64TargetLowering::LowerSETCCCARRY(SDValue Op,
11137 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
11363 SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
11402 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
11413 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
11493 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
11508 SDValue AArch64TargetLowering::LowerBR_JT(SDValue Op,
11551 SDValue AArch64TargetLowering::LowerBRIND(SDValue Op, SelectionDAG &DAG) const {
11578 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
11595 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
11630 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
11644 SDValue AArch64TargetLowering::LowerWin64_VASTART(SDValue Op,
11675 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
11754 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
11767 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
11787 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11857 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
11878 SDValue AArch64TargetLowering::LowerSPONENTRY(SDValue Op,
11893 Register AArch64TargetLowering::
11909 SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,
11923 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
11964 SDValue AArch64TargetLowering::LowerShiftParts(SDValue Op,
11971 bool AArch64TargetLowering::isOffsetFoldingLegal(
11978 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
12057 AArch64TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
12067 AArch64TargetLowering::getSqrtResultForDenormInput(SDValue Op,
12072 SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,
12104 SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
12157 const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
12301 SDValue AArch64TargetLowering::LowerAsmOutputForConstraint(
12334 AArch64TargetLowering::ConstraintType
12335 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
12374 AArch64TargetLowering::getSingleConstraintMatchWeight(
12407 AArch64TargetLowering::getRegForInlineAsmConstraint(
12515 EVT AArch64TargetLowering::getAsmOperandValueType(const DataLayout &DL,
12526 void AArch64TargetLowering::LowerAsmOperandForConstraint(
12785 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
12788 LLVM_DEBUG(dbgs() << "AArch64TargetLowering::ReconstructShuffle\n");
13825 AArch64TargetLowering::LowerZERO_EXTEND_VECTOR_INREG(SDValue Op,
13842 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
14035 SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op,
14066 SDValue AArch64TargetLowering::LowerDUPQLane(SDValue Op,
14510 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
14663 SDValue AArch64TargetLowering::LowerFixedLengthBuildVectorToSVE(
14722 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
15160 SDValue AArch64TargetLowering::LowerCONCAT_VECTORS(SDValue Op,
15197 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
15232 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
15284 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
15337 SDValue AArch64TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
15464 SDValue AArch64TargetLowering::LowerDIV(SDValue Op, SelectionDAG &DAG) const {
15515 bool AArch64TargetLowering::shouldExpandBuildVectorWithShuffles(
15522 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
15555 bool AArch64TargetLowering::isVectorClearMaskLegal(ArrayRef<int> M,
15603 SDValue AArch64TargetLowering::LowerTRUNCATE(SDValue Op,
15672 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
15853 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
16066 SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
16141 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
16161 AArch64TargetLowering::LowerWindowsDYNAMIC_STACKALLOC(SDValue Op,
16227 AArch64TargetLowering::LowerInlineDYNAMIC_STACKALLOC(SDValue Op,
16254 AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16266 SDValue AArch64TargetLowering::LowerAVG(SDValue Op, SelectionDAG &DAG,
16275 SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
16289 setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,
16290 AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) {
16314 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
16490 bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,
16525 bool AArch64TargetLowering::shouldRemoveRedundantExtend(SDValue Extend) const {
16541 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16548 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16559 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
16585 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16592 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16600 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16615 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
16852 bool AArch64TargetLowering::optimizeExtendOrTruncateConversion(
16984 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
16997 unsigned AArch64TargetLowering::getNumInterleavedAccesses(
17008 AArch64TargetLowering::getTargetMMOFlags(const Instruction &I) const {
17015 bool AArch64TargetLowering::isLegalInterleavedAccessType(
17135 bool AArch64TargetLowering::lowerInterleavedLoad(
17319 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
17469 bool AArch64TargetLowering::lowerDeinterleaveIntrinsicToLoad(
17543 bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore(
17607 EVT AArch64TargetLowering::getOptimalMemOpType(
17637 LLT AArch64TargetLowering::getOptimalMemOpLLT(
17668 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
17683 bool AArch64TargetLowering::isLegalAddScalableImmediate(int64_t Imm) const {
17718 bool AArch64TargetLowering::isMulAddWithConstProfitable(
17746 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
17752 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
17831 AArch64TargetLowering::getPreferredLargeGEPBaseOffset(int64_t MinOffset,
17842 bool AArch64TargetLowering::shouldConsiderGEPOffsetSplit() const {
17847 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(
17867 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
17878 bool AArch64TargetLowering::generateFMAsInMachineCombiner(
17885 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
17895 ArrayRef<MCPhysReg> AArch64TargetLowering::getRoundingControlRegisters() const {
17901 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
17938 bool AArch64TargetLowering::isDesirableToCommuteXorWithShift(
17962 bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
18001 bool AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(
18006 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
18028 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
18393 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
18423 AArch64TargetLowering::BuildSREMPow2(SDNode *N, const APInt &Divisor,
19182 const AArch64TargetLowering &TLI) {
19361 const AArch64TargetLowering &TLI) {
23290 const AArch64TargetLowering &TLI,
26388 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
26743 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
26780 bool AArch64TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
26784 bool AArch64TargetLowering::isIndexingLegal(MachineInstr &MI, Register Base,
26797 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *N, SDNode *Op,
26846 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
26867 bool AArch64TargetLowering::getPostIndexedAddressParts(
26934 void AArch64TargetLowering::ReplaceBITCASTResults(
27048 void AArch64TargetLowering::ReplaceExtractSubVectorResults(
27317 void AArch64TargetLowering::ReplaceNodeResults(
27557 bool AArch64TargetLowering::useLoadStackGuardNode(const Module &M) const {
27563 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
27570 AArch64TargetLowering::getPreferredVectorAction(MVT VT) const {
27582 bool AArch64TargetLowering::isOpSuitableForLDPSTP(const Instruction *I) const {
27597 bool AArch64TargetLowering::isOpSuitableForLSE128(const Instruction *I) const {
27619 bool AArch64TargetLowering::isOpSuitableForRCPC3(const Instruction *I) const {
27636 bool AArch64TargetLowering::shouldInsertFencesForAtomic(
27647 bool AArch64TargetLowering::shouldInsertTrailingFenceForAtomicStore(
27675 AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
27692 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
27743 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
27791 AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
27813 Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,
27855 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
27860 Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder,
27902 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
27916 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
27931 Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
27946 void AArch64TargetLowering::insertSSPDeclarations(Module &M) const {
27967 Value *AArch64TargetLowering::getSDagStackGuard(const Module &M) const {
27974 Function *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const {
27982 AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
27999 Register AArch64TargetLowering::getExceptionPointerRegister(
28007 Register AArch64TargetLowering::getExceptionSelectorRegister(
28013 bool AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial(
28026 bool AArch64TargetLowering::
28040 AArch64TargetLowering::preferredShiftLegalizationStrategy(
28049 void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
28055 void AArch64TargetLowering::insertCopiesSplitCSR(
28096 bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
28108 bool AArch64TargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
28123 bool AArch64TargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
28128 bool AArch64TargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
28139 bool AArch64TargetLowering::shouldExpandCmpUsingSelects(EVT VT) const {
28146 AArch64TargetLowering::EmitKCFICheck(MachineBasicBlock &MBB,
28174 bool AArch64TargetLowering::enableAggressiveFMAFusion(EVT VT) const {
28179 AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
28186 void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
28210 bool AArch64TargetLowering::needsFixedCatchObjects() const {
28214 bool AArch64TargetLowering::shouldLocalize(
28293 bool AArch64TargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
28436 SDValue AArch64TargetLowering::LowerFixedLengthVectorLoadToSVE(
28494 SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(
28545 SDValue AArch64TargetLowering::LowerFixedLengthVectorStoreToSVE(
28578 SDValue AArch64TargetLowering::LowerFixedLengthVectorMStoreToSVE(
28595 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE(
28661 SDValue AArch64TargetLowering::LowerFixedLengthVectorIntExtendToSVE(
28697 SDValue AArch64TargetLowering::LowerFixedLengthVectorTruncateToSVE(
28733 SDValue AArch64TargetLowering::LowerFixedLengthExtractVectorElt(
28746 SDValue AArch64TargetLowering::LowerFixedLengthInsertVectorElt(
28765 SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,
28822 SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,
28851 SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp,
28879 SDValue AArch64TargetLowering::LowerPredReductionToSVE(SDValue ReduceOp,
28922 SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
28970 AArch64TargetLowering::LowerFixedLengthVectorSelectToSVE(SDValue Op,
28994 SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
29019 AArch64TargetLowering::LowerFixedLengthBitcastToSVE(SDValue Op,
29033 SDValue AArch64TargetLowering::LowerFixedLengthConcatVectorsToSVE(
29068 AArch64TargetLowering::LowerFixedLengthFPExtendToSVE(SDValue Op,
29093 AArch64TargetLowering::LowerFixedLengthFPRoundToSVE(SDValue Op,
29117 AArch64TargetLowering::LowerFixedLengthIntToFPToSVE(SDValue Op,
29161 AArch64TargetLowering::LowerVECTOR_DEINTERLEAVE(SDValue Op,
29174 SDValue AArch64TargetLowering::LowerVECTOR_INTERLEAVE(SDValue Op,
29188 SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
29254 AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op,
29408 SDValue AArch64TargetLowering::LowerFixedLengthVECTOR_SHUFFLEToSVE(
29571 SDValue AArch64TargetLowering::getSVESafeBitCast(EVT VT, SDValue Op,
29628 bool AArch64TargetLowering::isAllActivePredicate(SelectionDAG &DAG,
29633 EVT AArch64TargetLowering::getPromotedVTForPredicate(EVT VT) const {
29637 bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
29715 bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
29723 bool AArch64TargetLowering::isComplexDeinterleavingSupported() const {
29728 bool AArch64TargetLowering::isComplexDeinterleavingOperationSupported(
29767 Value *AArch64TargetLowering::createComplexDeinterleavingIR(
29879 bool AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const {
29889 unsigned AArch64TargetLowering::getMinimumJumpTableEntries() const {
29893 MVT AArch64TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
29909 unsigned AArch64TargetLowering::getNumRegistersForCallingConv(
29923 unsigned AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(
29989 bool AArch64TargetLowering::hasInlineStackProbe(
29995 bool AArch64TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
30008 void AArch64TargetLowering::verifyTargetSDNode(const SDNode *N) const {