Lines Matching defs:Intrinsic

1499       Disc->getConstantOperandVal(0) == Intrinsic::ptrauth_blend) {
1867   SDNode *Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Ops);
1868   SDValue SuperReg = SDValue(Intrinsic, 0);
1921   SDNode *Intrinsic;
1923     Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped,
1926     Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Zdn, Zm);
1927   SDValue SuperReg = SDValue(Intrinsic, 0);
2080   SDNode *Intrinsic = CurDAG->getMachineNode(Op, DL, MVT::Untyped, Ops);
2081   SDValue SuperReg = SDValue(Intrinsic, 0);
4428       IRG_SP->getConstantOperandVal(1) != Intrinsic::aarch64_irg_sp) {
4734     case Intrinsic::aarch64_gcsss: {
4746     case Intrinsic::aarch64_ldaxp:
4747     case Intrinsic::aarch64_ldxp: {
4749           IntNo == Intrinsic::aarch64_ldaxp ? AArch64::LDAXPX : AArch64::LDXPX;
4764     case Intrinsic::aarch64_stlxp:
4765     case Intrinsic::aarch64_stxp: {
4767           IntNo == Intrinsic::aarch64_stlxp ? AArch64::STLXPX : AArch64::STXPX;
4786     case Intrinsic::aarch64_neon_ld1x2:
4813     case Intrinsic::aarch64_neon_ld1x3:
4840     case Intrinsic::aarch64_neon_ld1x4:
4867     case Intrinsic::aarch64_neon_ld2:
4894     case Intrinsic::aarch64_neon_ld3:
4921     case Intrinsic::aarch64_neon_ld4:
4948     case Intrinsic::aarch64_neon_ld2r:
4975     case Intrinsic::aarch64_neon_ld3r:
5002     case Intrinsic::aarch64_neon_ld4r:
5029     case Intrinsic::aarch64_neon_ld2lane:
5047     case Intrinsic::aarch64_neon_ld3lane:
5065     case Intrinsic::aarch64_neon_ld4lane:
5083     case Intrinsic::aarch64_ld64b:
5086     case Intrinsic::aarch64_sve_ld2q_sret: {
5090     case Intrinsic::aarch64_sve_ld3q_sret: {
5094     case Intrinsic::aarch64_sve_ld4q_sret: {
5098     case Intrinsic::aarch64_sve_ld2_sret: {
5119     case Intrinsic::aarch64_sve_ld1_pn_x2: {
5164     case Intrinsic::aarch64_sve_ld1_pn_x4: {
5209     case Intrinsic::aarch64_sve_ldnt1_pn_x2: {
5258     case Intrinsic::aarch64_sve_ldnt1_pn_x4: {
5307     case Intrinsic::aarch64_sve_ld3_sret: {
5328     case Intrinsic::aarch64_sve_ld4_sret: {
5349     case Intrinsic::aarch64_sme_read_hor_vg2: {
5370     case Intrinsic::aarch64_sme_read_ver_vg2: {
5391     case Intrinsic::aarch64_sme_read_hor_vg4: {
5412     case Intrinsic::aarch64_sme_read_ver_vg4: {
5433     case Intrinsic::aarch64_sme_read_vg1x2: {
5438     case Intrinsic::aarch64_sme_read_vg1x4: {
5443     case Intrinsic::aarch64_sme_readz_horiz_x2: {
5460     case Intrinsic::aarch64_sme_readz_vert_x2: {
5477     case Intrinsic::aarch64_sme_readz_horiz_x4: {
5494     case Intrinsic::aarch64_sme_readz_vert_x4: {
5511     case Intrinsic::aarch64_sme_readz_x2: {
5516     case Intrinsic::aarch64_sme_readz_x4: {
5521     case Intrinsic::swift_async_context_addr: {
5539     case Intrinsic::aarch64_sme_luti2_lane_zt_x4: {
5548     case Intrinsic::aarch64_sme_luti4_lane_zt_x4: {
5556     case Intrinsic::aarch64_sme_luti2_lane_zt_x2: {
5565     case Intrinsic::aarch64_sme_luti4_lane_zt_x2: {
5574     case Intrinsic::aarch64_sme_luti4_zt_x4: {
5578     case Intrinsic::aarch64_sve_fp8_cvtl1_x2:
5584     case Intrinsic::aarch64_sve_fp8_cvtl2_x2:
5590     case Intrinsic::aarch64_sve_fp8_cvt1_x2:
5596     case Intrinsic::aarch64_sve_fp8_cvt2_x2:
5609     case Intrinsic::aarch64_tagp:
5613     case Intrinsic::ptrauth_auth:
5617     case Intrinsic::ptrauth_resign:
5621     case Intrinsic::aarch64_neon_tbl2:
5626     case Intrinsic::aarch64_neon_tbl3:
5631     case Intrinsic::aarch64_neon_tbl4:
5636     case Intrinsic::aarch64_neon_tbx2:
5641     case Intrinsic::aarch64_neon_tbx3:
5646     case Intrinsic::aarch64_neon_tbx4:
5651     case Intrinsic::aarch64_sve_srshl_single_x2:
5658     case Intrinsic::aarch64_sve_srshl_single_x4:
5665     case Intrinsic::aarch64_sve_urshl_single_x2:
5672     case Intrinsic::aarch64_sve_urshl_single_x4:
5679     case Intrinsic::aarch64_sve_srshl_x2:
5686     case Intrinsic::aarch64_sve_srshl_x4:
5693     case Intrinsic::aarch64_sve_urshl_x2:
5700     case Intrinsic::aarch64_sve_urshl_x4:
5707     case Intrinsic::aarch64_sve_sqdmulh_single_vgx2:
5714     case Intrinsic::aarch64_sve_sqdmulh_single_vgx4:
5721     case Intrinsic::aarch64_sve_sqdmulh_vgx2:
5728     case Intrinsic::aarch64_sve_sqdmulh_vgx4:
5735     case Intrinsic::aarch64_sme_fp8_scale_single_x2:
5742     case Intrinsic::aarch64_sme_fp8_scale_single_x4:
5749     case Intrinsic::aarch64_sme_fp8_scale_x2:
5756     case Intrinsic::aarch64_sme_fp8_scale_x4:
5763     case Intrinsic::aarch64_sve_whilege_x2:
5770     case Intrinsic::aarch64_sve_whilegt_x2:
5777     case Intrinsic::aarch64_sve_whilehi_x2:
5784     case Intrinsic::aarch64_sve_whilehs_x2:
5791     case Intrinsic::aarch64_sve_whilele_x2:
5798     case Intrinsic::aarch64_sve_whilelo_x2:
5805     case Intrinsic::aarch64_sve_whilels_x2:
5812     case Intrinsic::aarch64_sve_whilelt_x2:
5819     case Intrinsic::aarch64_sve_smax_single_x2:
5826     case Intrinsic::aarch64_sve_umax_single_x2:
5833     case Intrinsic::aarch64_sve_fmax_single_x2:
5840     case Intrinsic::aarch64_sve_smax_single_x4:
5847     case Intrinsic::aarch64_sve_umax_single_x4:
5854     case Intrinsic::aarch64_sve_fmax_single_x4:
5861     case Intrinsic::aarch64_sve_smin_single_x2:
5868     case Intrinsic::aarch64_sve_umin_single_x2:
5875     case Intrinsic::aarch64_sve_fmin_single_x2:
5882     case Intrinsic::aarch64_sve_smin_single_x4:
5889     case Intrinsic::aarch64_sve_umin_single_x4:
5896     case Intrinsic::aarch64_sve_fmin_single_x4:
5903     case Intrinsic::aarch64_sve_smax_x2:
5910     case Intrinsic::aarch64_sve_umax_x2:
5917     case Intrinsic::aarch64_sve_fmax_x2:
5924     case Intrinsic::aarch64_sve_smax_x4:
5931     case Intrinsic::aarch64_sve_umax_x4:
5938     case Intrinsic::aarch64_sve_fmax_x4:
5945     case Intrinsic::aarch64_sme_famax_x2:
5952     case Intrinsic::aarch64_sme_famax_x4:
5959     case Intrinsic::aarch64_sme_famin_x2:
5966     case Intrinsic::aarch64_sme_famin_x4:
5973     case Intrinsic::aarch64_sve_smin_x2:
5980     case Intrinsic::aarch64_sve_umin_x2:
5987     case Intrinsic::aarch64_sve_fmin_x2:
5994     case Intrinsic::aarch64_sve_smin_x4:
6001     case Intrinsic::aarch64_sve_umin_x4:
6008     case Intrinsic::aarch64_sve_fmin_x4:
6015     case Intrinsic::aarch64_sve_fmaxnm_single_x2 :
6022     case Intrinsic::aarch64_sve_fmaxnm_single_x4 :
6029     case Intrinsic::aarch64_sve_fminnm_single_x2:
6036     case Intrinsic::aarch64_sve_fminnm_single_x4:
6043     case Intrinsic::aarch64_sve_fmaxnm_x2:
6050     case Intrinsic::aarch64_sve_fmaxnm_x4:
6057     case Intrinsic::aarch64_sve_fminnm_x2:
6064     case Intrinsic::aarch64_sve_fminnm_x4:
6071     case Intrinsic::aarch64_sve_fcvtzs_x2:
6074     case Intrinsic::aarch64_sve_scvtf_x2:
6077     case Intrinsic::aarch64_sve_fcvtzu_x2:
6080     case Intrinsic::aarch64_sve_ucvtf_x2:
6083     case Intrinsic::aarch64_sve_fcvtzs_x4:
6086     case Intrinsic::aarch64_sve_scvtf_x4:
6089     case Intrinsic::aarch64_sve_fcvtzu_x4:
6092     case Intrinsic::aarch64_sve_ucvtf_x4:
6095     case Intrinsic::aarch64_sve_fcvt_widen_x2:
6098     case Intrinsic::aarch64_sve_fcvtl_widen_x2:
6101     case Intrinsic::aarch64_sve_sclamp_single_x2:
6108     case Intrinsic::aarch64_sve_uclamp_single_x2:
6115     case Intrinsic::aarch64_sve_fclamp_single_x2:
6122     case Intrinsic::aarch64_sve_bfclamp_single_x2:
6125     case Intrinsic::aarch64_sve_sclamp_single_x4:
6132     case Intrinsic::aarch64_sve_uclamp_single_x4:
6139     case Intrinsic::aarch64_sve_fclamp_single_x4:
6146     case Intrinsic::aarch64_sve_bfclamp_single_x4:
6149     case Intrinsic::aarch64_sve_add_single_x2:
6156     case Intrinsic::aarch64_sve_add_single_x4:
6163     case Intrinsic::aarch64_sve_zip_x2:
6170     case Intrinsic::aarch64_sve_zipq_x2:
6174     case Intrinsic::aarch64_sve_zip_x4:
6181     case Intrinsic::aarch64_sve_zipq_x4:
6185     case Intrinsic::aarch64_sve_uzp_x2:
6192     case Intrinsic::aarch64_sve_uzpq_x2:
6196     case Intrinsic::aarch64_sve_uzp_x4:
6203     case Intrinsic::aarch64_sve_uzpq_x4:
6207     case Intrinsic::aarch64_sve_sel_x2:
6214     case Intrinsic::aarch64_sve_sel_x4:
6221     case Intrinsic::aarch64_sve_frinta_x2:
6224     case Intrinsic::aarch64_sve_frinta_x4:
6227     case Intrinsic::aarch64_sve_frintm_x2:
6230     case Intrinsic::aarch64_sve_frintm_x4:
6233     case Intrinsic::aarch64_sve_frintn_x2:
6236     case Intrinsic::aarch64_sve_frintn_x4:
6239     case Intrinsic::aarch64_sve_frintp_x2:
6242     case Intrinsic::aarch64_sve_frintp_x4:
6245     case Intrinsic::aarch64_sve_sunpk_x2:
6252     case Intrinsic::aarch64_sve_uunpk_x2:
6259     case Intrinsic::aarch64_sve_sunpk_x4:
6266     case Intrinsic::aarch64_sve_uunpk_x4:
6273     case Intrinsic::aarch64_sve_pext_x2: {
6291     case Intrinsic::aarch64_neon_st1x2: {
6321     case Intrinsic::aarch64_neon_st1x3: {
6351     case Intrinsic::aarch64_neon_st1x4: {
6381     case Intrinsic::aarch64_neon_st2: {
6411     case Intrinsic::aarch64_neon_st3: {
6441     case Intrinsic::aarch64_neon_st4: {
6471     case Intrinsic::aarch64_neon_st2lane: {
6490     case Intrinsic::aarch64_neon_st3lane: {
6509     case Intrinsic::aarch64_neon_st4lane: {
6528     case Intrinsic::aarch64_sve_st2q: {
6532     case Intrinsic::aarch64_sve_st3q: {
6536     case Intrinsic::aarch64_sve_st4q: {
6540     case Intrinsic::aarch64_sve_st2: {
6557     case Intrinsic::aarch64_sve_st3: {
6574     case Intrinsic::aarch64_sve_st4: {
7312   case Intrinsic::aarch64_sme_ldr:
7313   case Intrinsic::aarch64_sme_str:
7315   case Intrinsic::aarch64_sve_prf:
7320   case Intrinsic::aarch64_sve_ld2_sret:
7321   case Intrinsic::aarch64_sve_ld2q_sret:
7324   case Intrinsic::aarch64_sve_st2q:
7327   case Intrinsic::aarch64_sve_ld3_sret:
7328   case Intrinsic::aarch64_sve_ld3q_sret:
7331   case Intrinsic::aarch64_sve_st3q:
7334   case Intrinsic::aarch64_sve_ld4_sret:
7335   case Intrinsic::aarch64_sve_ld4q_sret:
7338   case Intrinsic::aarch64_sve_st4q:
7341   case Intrinsic::aarch64_sve_ld1udq:
7342   case Intrinsic::aarch64_sve_st1dq:
7344   case Intrinsic::aarch64_sve_ld1uwq:
7345   case Intrinsic::aarch64_sve_st1wq: