Lines Matching defs:SrcVT
198 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
258 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
261 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
264 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1190 MVT SrcVT = RetVT;
1216 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1296 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
2837 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2838 if (SrcVT == MVT::f128 || SrcVT == MVT::f16 || SrcVT == MVT::bf16)
2842 if (SrcVT == MVT::f64) {
2876 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2879 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2881 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2887 if (SrcVT == MVT::i64) {
3047 MVT SrcVT = ArgVT;
3048 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
3057 MVT SrcVT = ArgVT;
3058 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3963 MVT SrcVT = SrcEVT.getSimpleVT();
3966 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3967 SrcVT != MVT::i8)
3983 if (SrcVT == MVT::i64) {
4107 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4109 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4111 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4112 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4120 unsigned SrcBits = SrcVT.getSizeInBits();
4126 if (RetVT == SrcVT) {
4133 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4173 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4210 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4212 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4214 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4215 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4223 unsigned SrcBits = SrcVT.getSizeInBits();
4229 if (RetVT == SrcVT) {
4236 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4274 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4277 SrcVT = RetVT;
4278 SrcBits = SrcVT.getSizeInBits();
4289 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4326 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4328 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4330 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4331 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4339 unsigned SrcBits = SrcVT.getSizeInBits();
4345 if (RetVT == SrcVT) {
4352 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4394 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4406 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4410 // FastISel does not have plumbing to deal with extensions where the SrcVT or
4412 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4416 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
4417 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
4423 switch (SrcVT.SimpleTy) {
4516 MVT SrcVT) {
4544 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4573 MVT SrcVT;
4577 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
4581 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4592 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4607 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4674 MVT SrcVT = VT;
4680 SrcVT = VT;
4689 SrcVT = VT;
4701 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt);
4737 MVT SrcVT = RetVT;
4744 SrcVT = TmpVT;
4753 SrcVT = TmpVT;
4767 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4770 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4773 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4813 MVT RetVT, SrcVT;
4815 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
4821 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4823 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4825 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4827 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)