Lines Matching defs:SetFlags
204 const Value *RHS, bool SetFlags = false,
207 unsigned RHSReg, bool SetFlags = false,
210 uint64_t Imm, bool SetFlags = false,
214 uint64_t ShiftImm, bool SetFlags = false,
218 uint64_t ShiftImm, bool SetFlags = false,
236 bool SetFlags = false, bool WantResult = true,
240 bool SetFlags = false, bool WantResult = true,
1168 const Value *RHS, bool SetFlags,
1222 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1225 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1229 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1241 SetFlags, WantResult);
1260 ShiftVal, SetFlags, WantResult);
1283 ShiftVal, SetFlags, WantResult);
1298 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1302 unsigned RHSReg, bool SetFlags,
1320 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1339 uint64_t Imm, bool SetFlags,
1362 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1364 if (SetFlags)
1386 uint64_t ShiftImm, bool SetFlags,
1406 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1428 uint64_t ShiftImm, bool SetFlags,
1447 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1449 if (SetFlags)
1493 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1499 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1536 bool SetFlags, bool WantResult, bool IsZExt) {
1537 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1565 bool SetFlags, bool WantResult, bool IsZExt) {
1566 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1573 /*SetFlags=*/true, WantResult);
1581 ShiftImm, /*SetFlags=*/true, WantResult);
3699 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3703 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3707 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3711 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3730 AArch64_AM::SXTW, /*ShiftImm=*/0, /*SetFlags=*/true,