Lines Matching defs:RetVT
198 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
203 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
206 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
209 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
212 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
216 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
226 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
235 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
239 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
247 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
249 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
251 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
253 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
254 unsigned emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1);
255 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
256 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1);
257 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
258 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
260 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
261 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
263 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
264 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1167 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1172 switch (RetVT.SimpleTy) {
1190 MVT SrcVT = RetVT;
1191 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1216 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1222 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1225 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1229 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1240 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1259 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1282 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1296 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1298 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1301 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1310 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1319 bool Is64Bit = RetVT == MVT::i64;
1338 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1343 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1361 bool Is64Bit = RetVT == MVT::i64;
1383 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1392 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1396 if (ShiftImm >= RetVT.getSizeInBits())
1405 bool Is64Bit = RetVT == MVT::i64;
1425 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1434 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1446 bool Is64Bit = RetVT == MVT::i64;
1491 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1493 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1497 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm) {
1498 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, Imm,
1502 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1503 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1518 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1528 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1535 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1537 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1564 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1566 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1570 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1572 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1576 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1580 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1584 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1608 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1629 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1643 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1653 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1655 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1656 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1662 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1674 switch (RetVT.SimpleTy) {
1700 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1701 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1707 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1719 if (ShiftImm >= RetVT.getSizeInBits())
1724 switch (RetVT.SimpleTy) {
1742 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1743 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1749 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg,
1751 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, Imm);
1754 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1830 bool IsRet64Bit = RetVT == MVT::i64;
1879 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
1977 MVT RetVT = VT;
1981 if (isTypeSupported(ZE->getType(), RetVT))
1984 RetVT = VT;
1986 if (isTypeSupported(SE->getType(), RetVT))
1989 RetVT = VT;
1995 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
2018 if (RetVT == MVT::i64 && VT <= MVT::i32) {
3365 MVT RetVT;
3369 if (!isTypeLegal(RetTy, RetVT))
3372 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3546 MVT RetVT;
3547 if (!isTypeLegal(II->getType(), RetVT))
3550 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3559 bool Is64Bit = RetVT == MVT::f64;
4049 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4051 switch (RetVT.SimpleTy) {
4056 RetVT = MVT::i32;
4063 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4067 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4068 if (RetVT != MVT::i64)
4075 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, unsigned Op1) {
4076 if (RetVT != MVT::i64)
4083 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
4088 switch (RetVT.SimpleTy) {
4097 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4107 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4109 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4114 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4115 RetVT == MVT::i64) && "Unexpected return value type.");
4117 bool Is64Bit = (RetVT == MVT::i64);
4119 unsigned DstBits = RetVT.getSizeInBits();
4126 if (RetVT == SrcVT) {
4133 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4173 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4185 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
4190 switch (RetVT.SimpleTy) {
4199 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4210 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4212 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4217 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4218 RetVT == MVT::i64) && "Unexpected return value type.");
4220 bool Is64Bit = (RetVT == MVT::i64);
4222 unsigned DstBits = RetVT.getSizeInBits();
4229 if (RetVT == SrcVT) {
4236 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4269 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4274 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4277 SrcVT = RetVT;
4289 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4301 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
4306 switch (RetVT.SimpleTy) {
4315 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4317 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false);
4326 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4328 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4333 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4334 RetVT == MVT::i64) && "Unexpected return value type.");
4336 bool Is64Bit = (RetVT == MVT::i64);
4338 unsigned DstBits = RetVT.getSizeInBits();
4345 if (RetVT == SrcVT) {
4352 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4385 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4394 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4515 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4544 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4572 MVT RetVT;
4574 if (!isTypeSupported(I->getType(), RetVT))
4581 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4592 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4607 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4727 MVT RetVT;
4728 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4731 if (RetVT.isVector())
4737 MVT SrcVT = RetVT;
4767 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4770 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4773 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4795 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4798 ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4801 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4813 MVT RetVT, SrcVT;
4817 if (!isTypeLegal(I->getType(), RetVT))
4821 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4823 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4825 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4827 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4833 switch (RetVT.SimpleTy) {
4853 MVT RetVT;
4854 if (!isTypeLegal(I->getType(), RetVT))
4858 switch (RetVT.SimpleTy) {