Lines Matching defs:Op0Reg

257   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
258   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
260   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
261   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
263   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, unsigned Op1Reg);
264   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
3638     Register Op0Reg = getRegForValue(II->getOperand(0));
3639     if (!Op0Reg)
3642     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
4083 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg,
4101   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4185 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg,
4201     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Mask);
4204   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4301 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg,
4317     Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false);
4320   Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4760     Register Op0Reg = getRegForValue(Op0);
4761     if (!Op0Reg)
4767       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4770       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4773       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4783   Register Op0Reg = getRegForValue(I->getOperand(0));
4784   if (!Op0Reg)
4795     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4798     ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4801     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4840   Register Op0Reg = getRegForValue(I->getOperand(0));
4841   if (!Op0Reg)
4844   Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg);