Lines Matching defs:DestVT

233   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
234   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2829   MVT DestVT;
2830   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2844       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2846       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2849       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2851       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2854       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2862   MVT DestVT;
2863   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2866   if (DestVT == MVT::f16 || DestVT == MVT::bf16)
2869   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2889       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2891       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2894       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2896       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2899   Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
3046       MVT DestVT = VA.getLocVT();
3048       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
3056       MVT DestVT = VA.getLocVT();
3058       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3916     MVT DestVT = VA.getValVT();
3918     if (RVVT != DestVT) {
3926       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3964   MVT DestVT = DestEVT.getSimpleVT();
3969   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3970       DestVT != MVT::i1)
3985     switch (DestVT.SimpleTy) {
4016 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4017   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4018           DestVT == MVT::i64) &&
4021   if (DestVT == MVT::i8 || DestVT == MVT::i16)
4022     DestVT = MVT::i32;
4027     if (DestVT == MVT::i64) {
4040     if (DestVT == MVT::i64) {
4406 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4408   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4411   // DestVT are odd things, so test to make sure that they are both types we can
4412   // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4414   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4415        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4427     return emiti1Ext(SrcReg, DestVT, IsZExt);
4429     if (DestVT == MVT::i64)
4436     if (DestVT == MVT::i64)
4443     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4450   if (DestVT == MVT::i8 || DestVT == MVT::i16)
4451     DestVT = MVT::i32;
4452   else if (DestVT == MVT::i64) {
4463       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4620   MVT DestVT = DestEVT.getSimpleVT();
4621   if (DestVT != MVT::i64 && DestVT != MVT::i32)
4625   bool Is64bit = (DestVT == MVT::i64);
4646       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;