Lines Matching defs:CmpMI

155   MachineInstr *CmpMI;
185   bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
378 /// Only CmpMI is allowed to clobber the flags.
381                                      const MachineInstr *CmpMI) {
424     // Only CmpMI is allowed to clobber the flags.
425     if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
556   CmpMI = findConvertibleCompare(CmpBB);
557   if (!CmpMI)
560   if (!canSpeculateInstrs(CmpBB, CmpMI)) {
647   // Now replace CmpMI with a ccmp instruction that also considers the incoming
650   unsigned FirstOp = 1;   // First CmpMI operand to copy.
651   bool isZBranch = false; // CmpMI is a cbz/cbnz instruction.
652   switch (CmpMI->getOpcode()) {
688   MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
690   if (CmpMI->getOperand(FirstOp + 1).isReg())
691     MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
693   MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
694                                 .add(CmpMI->getOperand(FirstOp)); // Register Rn
698     MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
701   // If CmpMI was a terminator, we need a new conditional branch to replace it.
704     bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
705                 CmpMI->getOpcode() == AArch64::CBNZX;
706     BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
708         .add(CmpMI->getOperand(1)); // Branch target.
710   CmpMI->eraseFromParent();
740   switch (CmpMI->getOpcode()) {