Lines Matching +full:0 +full:xb
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
20 // L2: add xB, xA, sym@PAGEOFF
21 // L3: ldr xC, [xB, #imm]
29 // L3: ldr xC, [xB, sym@PAGEOFF + #imm]
32 // L3: ldr xC, [xB, #imm]
44 // - The base address (xB) in L3 is defined only L2.
52 // L2: add xB, xA, sym@PAGEOFF
53 // L3: ldr xC, [xB, #imm]
56 // L2: ldr xB, [xA, sym@GOTPAGEOFF]
57 // L3: ldr xC, [xB, #imm]
63 // L2: add xB, xA, sym@PAGEOFF
64 // L3: str xC, [xB, #imm]
67 // L2: ldr xB, [xA, sym@GOTPAGEOFF]
68 // L3: str xC, [xB, #imm]
71 // L2: add xB, xA, sym@PAGEOFF
147 char AArch64CollectLOH::ID = 0;
208 // even if #imm == 0.
210 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
253 /// Map register number to index from 0-30.
397 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg());
398 int OpIdx = mapRegToGPRIndex(AddMI->getOperand(0).getReg());
489 if (Idx >= 0)
507 if (Idx < 0)
518 if (Idx < 0)
541 memset(LOHInfos, 0, sizeof(LOHInfos));
546 if (RegIdx >= 0)
561 const MachineOperand &Def = MI.getOperand(0);
567 if (DefIdx >= 0 && OpIdx >= 0 &&
573 const MachineOperand &Op0 = MI.getOperand(0);
575 if (Idx >= 0) {