Lines Matching +full:- +full:- +full:require +full:- +full:hashes
1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to the AArch64 assembly language.
12 //===----------------------------------------------------------------------===//
74 "aarch64-ptrauth-auth-checks", cl::Hidden,
82 "aarch64-win-import-call-optimization", cl::Hidden,
86 #define DEBUG_TYPE "asm-printer"
198 // Emit the sequence for LOADgotPAC/MOVaddrPAC (either GOT adrp-ldr or
199 // adrp-add followed by PAC sign)
207 /// tblgen'erated driver function for lowering simple MI->MC
235 if (STI->isTargetCOFF()) {
242 OutStreamer->beginCOFFSymbolDef(CurrentFnSym);
243 OutStreamer->emitCOFFSymbolStorageClass(Scl);
244 OutStreamer->emitCOFFSymbolType(Type);
245 OutStreamer->endCOFFSymbolDef();
322 MCSymbol *S = MMI->getContext().getOrCreateSymbol(StringRef("@feat.00"));
323 OutStreamer->beginCOFFSymbolDef(S);
324 OutStreamer->emitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_STATIC);
325 OutStreamer->emitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_NULL);
326 OutStreamer->endCOFFSymbolDef();
330 // Object is CFG-aware.
339 if (M.getModuleFlag("ms-kernel")) {
344 OutStreamer->emitSymbolAttribute(S, MCSA_Global);
345 OutStreamer->emitAssignment(
346 S, MCConstantExpr::create(Feat00Value, MMI->getContext()));
354 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
355 // Assemble feature flags that may require creation of build attributes and a
360 M.getModuleFlag("branch-target-enforcement"))) {
361 if (!BTE->isZero()) {
368 M.getModuleFlag("guarded-control-stack"))) {
369 if (!GCS->isZero()) {
376 M.getModuleFlag("sign-return-address"))) {
377 if (!Sign->isZero()) {
383 uint64_t PAuthABIPlatform = -1;
385 M.getModuleFlag("aarch64-elf-pauthabi-platform"))) {
386 PAuthABIPlatform = PAP->getZExtValue();
389 uint64_t PAuthABIVersion = -1;
391 M.getModuleFlag("aarch64-elf-pauthabi-version"))) {
392 PAuthABIVersion = PAV->getZExtValue();
398 TS->emitNoteSection(GNUFlags, PAuthABIPlatform, PAuthABIVersion);
402 const AArch64FunctionInfo *FI = MF->getInfo<AArch64FunctionInfo>();
403 std::optional<std::string> OutlinerString = FI->getOutliningStyle();
405 OutStreamer->getCommentOS() << ' ' << OutlinerString;
410 const Function &F = MF->getFunction();
411 if (F.hasFnAttribute("patchable-function-entry")) {
413 if (F.getFnAttribute("patchable-function-entry")
445 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
454 OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo());
456 OutStreamer->emitLabel(CurSled);
460 // The operand has to be the number of 4-byte instructions to jump over,
467 OutStreamer->emitLabel(Target);
476 PAuthABIPlatform = (uint64_t(-1) == PAuthABIPlatform) ? 0 : PAuthABIPlatform;
477 PAuthABIVersion = (uint64_t(-1) == PAuthABIVersion) ? 0 : PAuthABIVersion;
480 TS->emitAtributesSubsection(
484 TS->emitAttribute(
487 TS->emitAttribute(
497 TS->emitAtributesSubsection(AArch64BuildAttrs::getVendorName(
501 TS->emitAttribute(AArch64BuildAttrs::getVendorName(
504 TS->emitAttribute(AArch64BuildAttrs::getVendorName(
507 TS->emitAttribute(AArch64BuildAttrs::getVendorName(
514 // (built-in functions __xray_customevent/__xray_typedevent).
547 .addImm(-4));
577 .addImm(-2));
595 assert(std::next(MI.getIterator())->isCall() &&
597 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
600 // Default to using the intra-procedure-call temporary registers for
601 // comparing the hashes.
610 // with AArch64::TCRETURNriBTI), we can clobber another caller-saved
622 // Adjust the offset for patchable-function-prefix. This assumes that
623 // patchable-function-prefix is the same for all functions.
626 ->getFunction()
627 .getFnAttribute("patchable-function-prefix")
635 .addImm(-(PrefixNops * 4 + 4)));
643 // Compare the hashes and trap if there's a mismatch.
657 // 0-9 as follows:
658 // - 0-4: n, where the register Xn contains the target address
659 // - 5-9: m, where the register Wm contains the expected type hash
661 unsigned TypeIndex = ScratchRegs[1] - AArch64::W0;
665 AddrIndex = AddrReg - AArch64::X0;
679 OutStreamer->emitLabel(Pass);
689 // convert into a statically known-null pointer.
707 // FIXME: Make this work on non-ELF.
711 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
734 this->STI = static_cast<const AArch64Subtarget *>(&*STI);
765 OutStreamer->switchSection(OutContext.getELFSection(
767 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(),
770 OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
771 OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
772 OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
773 OutStreamer->emitLabel(Sym);
783 // Fortuitously, kShadowBaseAlignment == 32, so we use the 32-bit
784 // left-shift option in the MOV instruction. Combined with the 16-bit
813 OutStreamer->emitLabel(ReturnSym);
815 OutStreamer->emitLabel(HandleMismatchOrPartialSym);
854 .addImm(Size - 1)
885 OutStreamer->emitLabel(HandleMismatchSym);
893 .addImm(-32));
929 this->STI = nullptr;
947 MMI->getObjFileInfo<MachineModuleInfoMachO>();
953 OutStreamer->switchSection(
961 OutStreamer->addBlankLine();
969 OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
974 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
980 OutStreamer->switchSection(TLOF.getDataSection());
986 OutStreamer->addBlankLine();
995 // https://github.com/ARM-software/abi-aa/blob/main/pauthabielf64/pauthabielf64.rst#default-signing-schema
997 M.getModuleFlag("ptrauth-elf-got"));
998 if (PtrAuthELFGOTFlag && PtrAuthELFGOTFlag->getZExtValue() == 1)
1002 OutStreamer->emitSymbolAttribute(getSymbol(&GV),
1012 OutStreamer->switchSection(getObjFileLowering().getImportCallSection());
1016 OutStreamer->emitBytes(StringRef{ImpCallMagic, sizeof(ImpCallMagic)});
1031 OutStreamer->emitInt32(SectionSize);
1032 OutStreamer->emitCOFFSecNumber(Section->getBeginSymbol());
1035 OutStreamer->emitInt32(0x13);
1036 OutStreamer->emitCOFFSecOffset(CallsiteSymbol);
1037 OutStreamer->emitCOFFSymbolIndex(CalledSymbol);
1046 for (const auto &D : AArch64FI->getLOHContainer()) {
1051 MCArgs.push_back(LabelIt->second);
1053 OutStreamer->emitLOHDirective(D.getKind(), MCArgs);
1059 if (!AArch64FI->getLOHRelated().empty())
1063 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
1065 // Darwin uses a linker-private symbol name for constant-pools (to
1078 const MachineOperand &MO = MI->getOperand(OpNum);
1099 Sym->print(O, MAI);
1133 const TargetRegisterInfo *RI = STI->getRegisterInfo();
1135 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
1136 if (!RI->regsOverlap(RegToPrint, Reg))
1144 const MachineOperand &MO = MI->getOperand(OpNum);
1248 const MachineOperand &MO = MI->getOperand(OpNum);
1256 unsigned NOps = MI->getNumOperands();
1258 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1260 OS << MI->getDebugVariable()->getName();
1261 OS << " <- ";
1262 // Frame address. Currently handles register +- offset only.
1263 assert(MI->isIndirectDebugValue());
1265 for (unsigned I = 0, E = std::distance(MI->debug_operands().begin(),
1266 MI->debug_operands().end());
1274 printOperand(MI, NOps - 2, OS);
1278 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1281 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1285 MCSection *ReadOnlySec = TLOF.getSectionForJumpTable(MF->getFunction(), TM);
1286 OutStreamer->switchSection(ReadOnlySec);
1288 auto AFI = MF->getInfo<AArch64FunctionInfo>();
1295 unsigned Size = AFI->getJumpTableEntrySize(JTI);
1297 OutStreamer->emitLabel(GetJTISymbol(JTI));
1299 const MCSymbol *BaseSym = AArch64FI->getJumpTableEntryPCRelSymbol(JTI);
1304 MCSymbolRefExpr::create(JTBB->getSymbol(), OutContext);
1307 // .byte/.hword (LBB - Lbase)>>2
1309 // .word LBB - Lbase
1315 OutStreamer->emitValue(Value, Size);
1325 const auto AFI = MF->getInfo<AArch64FunctionInfo>();
1326 const auto Base = AArch64FI->getJumpTableEntryPCRelSymbol(JTI);
1328 switch (AFI->getJumpTableEntrySize(JTI)) {
1345 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall ||
1346 MF->getFunction().getCallingConv() ==
1348 MF->getInfo<AArch64FunctionInfo>()->isSVECC()) {
1350 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
1351 TS->emitDirectiveVariantPCS(CurrentFnSym);
1357 !MF->getFunction().hasLocalLinkage()) {
1361 OutStreamer->emitSymbolAttribute(Src, MCSA_WeakAntiDep);
1362 OutStreamer->emitAssignment(
1364 MMI->getContext()));
1369 if (MDNode *Node = MF->getFunction().getMetadata(Name)) {
1370 StringRef NameStr = cast<MDString>(Node->getOperand(0))->getString();
1371 Sym = MMI->getContext().getOrCreateSymbol(NameStr);
1398 if (CPA->hasAddressDiscriminator() &&
1399 !CPA->hasSpecialAddressDiscriminator(
1419 if (MDNode *Node = F->getMetadata("arm64ec_exp_name")) {
1420 StringRef ExpStr = cast<MDString>(Node->getOperand(0))->getString();
1421 MCSymbol *ExpSym = MMI->getContext().getOrCreateSymbol(ExpStr);
1422 MCSymbol *Sym = MMI->getContext().getOrCreateSymbol(GA.getName());
1424 OutStreamer->beginCOFFSymbolDef(ExpSym);
1425 OutStreamer->emitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_EXTERNAL);
1426 OutStreamer->emitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION
1428 OutStreamer->endCOFFSymbolDef();
1430 OutStreamer->beginCOFFSymbolDef(Sym);
1431 OutStreamer->emitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_EXTERNAL);
1432 OutStreamer->emitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION
1434 OutStreamer->endCOFFSymbolDef();
1435 OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
1436 OutStreamer->emitAssignment(
1438 MMI->getContext()));
1446 /// from the lowest-addressed possible destination to the desired basic
1447 /// block. Since all instructions are 4-byte aligned, this is further compressed
1459 STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
1463 int Size = AArch64FI->getJumpTableEntrySize(JTIdx);
1468 MF->getInfo<AArch64FunctionInfo>()->getJumpTableEntryPCRelSymbol(JTIdx);
1473 Label = MF->getContext().createTempSymbol();
1474 AArch64FI->setJumpTableEntryInfo(JTIdx, Size, Label);
1478 auto LabelExpr = MCSymbolRefExpr::create(Label, MF->getContext());
1483 // Load the number of instruction-steps to offset from the label.
1510 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1511 assert(MJTI && "Can't lower jump-table dispatch without JTI");
1513 const std::vector<MachineJumpTableEntry> &JTs = MJTI->getJumpTables();
1514 assert(!JTs.empty() && "Invalid JT index for jump-table dispatch");
1518 // cmp x16, x17 ; or #imm if table size fits in 12-bit
1533 assert(!AArch64FI->getJumpTableEntryPCRelSymbol(JTI) &&
1538 // cmp only supports a 12-bit immediate. If we need more, materialize the
1540 uint64_t MaxTableEntry = NumTableEntries - 1;
1600 MCSymbol *AdrLabel = MF->getContext().createTempSymbol();
1601 const auto *AdrLabelE = MCSymbolRefExpr::create(AdrLabel, MF->getContext());
1602 AArch64FI->setJumpTableEntryInfo(JTI, 4, AdrLabel);
1604 OutStreamer->emitLabel(AdrLabel);
1621 assert(STI->hasMOPS());
1622 assert(STI->hasMTE() || Opcode != AArch64::MOPSMemorySetTaggingPseudo);
1624 const auto Ops = [Opcode]() -> std::array<unsigned, 3> {
1671 if (MII == MBB.end() || MII->isCall() ||
1672 MII->getOpcode() == AArch64::DBG_VALUE ||
1673 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
1674 MII->getOpcode() == TargetOpcode::STACKMAP)
1677 NumNOPBytes -= 4;
1713 assert((NumBytes - EncodedBytes) % 4 == 0 &&
1767 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1771 auto &Ctx = OutStreamer->getContext();
1773 OutStreamer->emitLabel(FaultingLabel);
1791 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1824 if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround() &&
1825 STI->isNeonAvailable()) {
1828 DestReg = AArch64::D0 + (DestReg - AArch64::H0);
1830 DestReg = AArch64::D0 + (DestReg - AArch64::S0);
1844 FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr);
1845 if (!STI->hasFullFP16())
1846 DestReg = (AArch64::S0 + (DestReg - AArch64::H0));
1875 // just use the address discriminator register as-is (XZR or not).
1910 // - checked and clearing:
1923 // - checked and trapping:
1964 "XPACHint mode is only compatible with I-keys");
2003 // Non-trapping checked sequences return the stripped result in TestedReg,
2004 // skipping over success-only code (such as re-signing the pointer) if
2007 // the high bits of the re-signed value).
2016 // LR is already XPAC-ed at this point.
2023 // If Xtested was not XPAC-ed so far, emit XPAC here.
2040 OutStreamer->emitLabel(SuccessSym);
2045 // Otherwise, the callee may re-sign the invalid return address,
2048 if (!AArch64FI->shouldSignReturnAddress(*MF))
2051 auto LRCheckMethod = STI->getAuthenticatedLRCheckMethod(*MF);
2055 const AArch64RegisterInfo *TRI = STI->getRegisterInfo();
2057 TC->readsRegister(AArch64::X16, TRI) ? AArch64::X17 : AArch64::X16;
2058 assert(!TC->readsRegister(ScratchReg, TRI) &&
2061 AArch64FI->shouldSignWithBKey() ? AArch64PACKey::IB : AArch64PACKey::IA;
2068 const bool IsAUTPAC = MI->getOpcode() == AArch64::AUTPAC;
2084 bool ShouldTrap = MF->getFunction().hasFnAttribute("ptrauth-auth-traps");
2088 if (STI->hasFPAC())
2091 // However, command-line flags can override this, for experimentation.
2107 auto AUTKey = (AArch64PACKey::ID)MI->getOperand(0).getImm();
2108 uint64_t AUTDisc = MI->getOperand(1).getImm();
2109 unsigned AUTAddrDisc = MI->getOperand(2).getReg();
2128 // Unchecked or checked-but-non-trapping AUT is just an "AUT": we're done.
2143 // We already emitted unchecked and checked-but-non-trapping AUTs.
2149 auto PACKey = (AArch64PACKey::ID)MI->getOperand(3).getImm();
2150 uint64_t PACDisc = MI->getOperand(4).getImm();
2151 unsigned PACAddrDisc = MI->getOperand(5).getReg();
2172 OutStreamer->emitLabel(EndSym);
2176 bool IsCall = MI->getOpcode() == AArch64::BLRA;
2177 unsigned BrTarget = MI->getOperand(0).getReg();
2179 auto Key = (AArch64PACKey::ID)MI->getOperand(1).getImm();
2183 uint64_t Disc = MI->getOperand(2).getImm();
2186 unsigned AddrDisc = MI->getOperand(3).getReg();
2196 // implicit-def'ed by the MI and AddrDisc is not used as any other input, so
2231 const Value *BaseGV = CPA.getPointer()->stripAndAccumulateConstantOffsets(
2239 BaseGV->getContext().emitError(
2251 Sym, MCConstantExpr::create((-Offset).getSExtValue(), Ctx), Ctx);
2253 uint64_t KeyID = CPA.getKey()->getZExtValue();
2261 uint64_t Disc = CPA.getDiscriminator()->getZExtValue();
2294 "non-zero offset for $auth_ptr$ stub slots is not supported");
2305 "non-zero offset for $auth_ptr$ stub slots is not supported");
2332 ->getParent()
2333 ->getInfo<AArch64FunctionInfo>()
2334 ->hasELFSignedGOT();
2350 // - via GOT:
2351 // - unsigned GOT:
2355 // - ELF signed GOT:
2363 // - direct:
2369 // - abs(offset) fits 24 bits:
2371 // - abs(offset) does not fit 24 bits:
2372 // - offset < 0:
2376 // - offset > 0:
2382 // - 0 discriminator:
2384 // - Non-0 discriminator, no address discriminator:
2387 // - address discriminator (with potentially folded immediate discriminator):
2422 assert(GAOp.getGlobal()->getValueType() != nullptr);
2423 unsigned AuthOpcode = GAOp.getGlobal()->getValueType()->isFunctionTy()
2432 if (!STI->hasFPAC()) {
2456 const uint64_t AbsOffset = (Offset > 0 ? Offset : -((uint64_t)Offset));
2474 auto NeedMovk = [IsNeg, UOffset](int BitPos) -> bool {
2479 for (int I = 0; I != 64 - BitPos; I += 16)
2507 Register AuthResultReg = STI->hasFPAC() ? DstReg : AArch64::X16;
2511 if (MI.getMF()->getTarget().getCodeModel() == CodeModel::Tiny) {
2547 if (GAMO.getGlobal()->hasExternalWeakLinkage()) {
2555 assert(GAMO.getGlobal()->getValueType() != nullptr);
2556 unsigned AuthOpcode = GAMO.getGlobal()->getValueType()->isFunctionTy()
2564 if (GAMO.getGlobal()->hasExternalWeakLinkage())
2565 OutStreamer->emitLabel(UndefWeakSym);
2567 if (!STI->hasFPAC()) {
2586 STI->getPtrAuthBlockAddressDiscriminatorIfEnabled(Fn))
2593 // Simple pseudo-instructions have their lowering (with expansion to real
2594 // instructions) auto-generated.
2605 AArch64_MC::verifyInstructionPredicates(MI->getOpcode(), STI->getFeatureBits());
2610 assert(STI->getInstrInfo()->getInstSizeInBytes(*MI) >= InstsEmitted * 4);
2614 // Do any auto-generated pseudo lowerings.
2620 if (MI->getOpcode() == AArch64::ADRP) {
2621 for (auto &Opd : MI->operands()) {
2629 if (AArch64FI->getLOHRelated().count(MI)) {
2634 OutStreamer->emitLabel(LOHLabel);
2638 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
2640 switch (MI->getOpcode()) {
2647 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
2648 // non-empty. If MI is the initial BTI, place the
2652 MI == &MF->front().front()) {
2653 int64_t Imm = MI->getOperand(0).getImm();
2659 OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym);
2666 Register DestReg = MI->getOperand(0).getReg();
2667 const MachineOperand &MO_Sym = MI->getOperand(1);
2699 // The floating-point version doesn't quite work in rare cases on older
2701 if (STI->hasZeroCycleZeroingFPWorkaround() &&
2702 MI->getOperand(1).getImm() == 0) {
2705 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
2706 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
2714 if (isVerbose() && OutStreamer->hasRawTextSupport()) {
2718 OutStreamer->emitRawText(StringRef(OS.str()));
2723 ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
2731 OutStreamer->emitCFIBKeyFrame();
2736 ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
2742 OutStreamer->emitCFIMTETaggedFrame();
2769 // Tail calls use pseudo instructions so they have the proper code-gen
2774 Register Callee = MI->getOperand(0).getReg();
2775 const uint64_t Key = MI->getOperand(2).getImm();
2777 "Invalid auth key for tail-call return");
2779 const uint64_t Disc = MI->getOperand(3).getImm();
2782 Register AddrDisc = MI->getOperand(4).getReg();
2817 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
2825 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
2859 const MachineOperand &MO_Sym = MI->getOperand(0);
2908 const MachineOperand &MO_Sym = MI->getOperand(0);
2924 if (STI->isTargetILP32()) {
2937 if (STI->isTargetILP32()) {
2950 // Emit a relocation-annotation. This expands to no code, but requests
2957 --InstsEmitted; // no code emitted
3031 TS->emitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
3035 TS->emitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
3039 assert(MI->getOperand(0).getImm() < 0 &&
3041 TS->emitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
3045 TS->emitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
3046 MI->getOperand(1).getImm());
3050 assert(MI->getOperand(1).getImm() < 0 &&
3052 TS->emitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
3053 -MI->getOperand(1).getImm());
3057 if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 &&
3058 MI->getOperand(0).getImm() <= 28) {
3059 assert((MI->getOperand(0).getImm() - 19) % 2 == 0 &&
3061 TS->emitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(),
3062 MI->getOperand(2).getImm());
3065 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
3066 "Non-consecutive registers not allowed for save_regp");
3067 TS->emitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
3068 MI->getOperand(2).getImm());
3072 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
3073 "Non-consecutive registers not allowed for save_regp_x");
3074 assert(MI->getOperand(2).getImm() < 0 &&
3076 TS->emitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
3077 -MI->getOperand(2).getImm());
3081 TS->emitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
3082 MI->getOperand(1).getImm());
3086 assert(MI->getOperand(1).getImm() < 0 &&
3088 TS->emitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
3089 -MI->getOperand(1).getImm());
3093 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
3094 "Non-consecutive registers not allowed for save_regp");
3095 TS->emitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
3096 MI->getOperand(2).getImm());
3100 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
3101 "Non-consecutive registers not allowed for save_regp_x");
3102 assert(MI->getOperand(2).getImm() < 0 &&
3104 TS->emitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
3105 -MI->getOperand(2).getImm());
3109 TS->emitARM64WinCFISetFP();
3113 TS->emitARM64WinCFIAddFP(MI->getOperand(0).getImm());
3117 TS->emitARM64WinCFINop();
3121 TS->emitARM64WinCFIPrologEnd();
3125 TS->emitARM64WinCFIEpilogStart();
3129 TS->emitARM64WinCFIEpilogEnd();
3133 TS->emitARM64WinCFIPACSignLR();
3137 assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 &&
3138 "Non-consecutive registers not allowed for save_any_reg");
3139 assert(MI->getOperand(2).getImm() >= 0 &&
3140 "SaveAnyRegQP SEH opcode offset must be non-negative");
3141 assert(MI->getOperand(2).getImm() <= 1008 &&
3143 TS->emitARM64WinCFISaveAnyRegQP(MI->getOperand(0).getImm(),
3144 MI->getOperand(2).getImm());
3148 assert(MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1 &&
3149 "Non-consecutive registers not allowed for save_any_reg");
3150 assert(MI->getOperand(2).getImm() < 0 &&
3152 assert(MI->getOperand(2).getImm() >= -1008 &&
3154 TS->emitARM64WinCFISaveAnyRegQPX(MI->getOperand(0).getImm(),
3155 -MI->getOperand(2).getImm());
3179 auto [GV, OpFlags] = BranchInst->getMF()->tryGetCalledGlobal(BranchInst);
3180 if (GV && GV->hasDLLImportStorageClass()) {
3181 auto *CallSiteSymbol = MMI->getContext().createNamedTempSymbol("impcall");
3182 OutStreamer->emitLabel(CallSiteSymbol);
3185 SectionToImportedFunctionCalls[OutStreamer->getCurrentSectionOnly()]
3240 // minimum size by using the pre-indexed store variants, which saves a few
3244 // stp fp, lr, [sp, #-16]!
3246 // stp x1, x0, [sp, #-16]!
3247 // stp x3, x2, [sp, #-16]!
3248 // stp x5, x4, [sp, #-16]!
3249 // stp x7, x6, [sp, #-16]!
3250 // stp d1, d0, [sp, #-16]!
3251 // stp d3, d2, [sp, #-16]!
3252 // stp d5, d4, [sp, #-16]!
3253 // stp d7, d6, [sp, #-16]!
3275 .addImm(-2));
3289 .addImm(-2));
3297 .addImm(-2));
3309 MachineOperand::CreateES(LazyPointer->getName().data() + 1,
3323 MachineOperand::CreateES(LazyPointer->getName().data() + 1,
3342 for (int I = 3; I != -1; --I)
3350 for (int I = 3; I != -1; --I)