Lines Matching defs:IR

40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
42       Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());
55   LSUnit::Status LSS = LSU.isAvailable(IR);
71     InstRef &IR,
73   Instruction *IS = IR.getInstruction();
82   IS->execute(IR.getSourceIndex());
87     LSU.onInstructionIssued(IR);
94     IssuedSet.emplace_back(IR);
96     LSU.onInstructionExecuted(IR);
101     InstRef &IR,
105   const Instruction &Inst = *IR.getInstruction();
107   HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR);
110   issueInstructionImpl(IR, UsedResources);
125     InstRef &IR = *I;
126     if (!IR)
130     Instruction &IS = *IR.getInstruction();
136     if (IS.isMemOp() && !LSU.isReady(IR)) {
141     LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
144     Ready.emplace_back(IR);
145     ReadySet.emplace_back(IR);
147     IR.invalidate();
161     InstRef &IR = *I;
162     if (!IR)
167     Instruction &IS = *IR.getInstruction();
173     if (IS.isMemOp() && LSU.isWaiting(IR)) {
178     LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
181     Pending.emplace_back(IR);
182     PendingSet.emplace_back(IR);
184     IR.invalidate();
196     InstRef &IR = ReadySet[I];
198         Strategy->compare(IR, ReadySet[QueueIndex])) {
199       Instruction &IS = *IR.getInstruction();
213   InstRef IR = ReadySet[QueueIndex];
216   return IR;
222     InstRef &IR = *I;
223     if (!IR)
225     Instruction &IS = *IR.getInstruction();
227       LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
233     // Instruction IR has completed execution.
234     LSU.onInstructionExecuted(IR);
235     Executed.emplace_back(IR);
237     IR.invalidate();
252   for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
253     const Instruction &IS = *IR.getInstruction();
257     if (IS.isMemOp() && LSU.isPending(IR))
258       MemDeps.emplace_back(IR);
261       RegDeps.emplace_back(IR);
274   for (InstRef &IR : IssuedSet)
275     IR.getInstruction()->cycleEvent();
278   for (InstRef &IR : PendingSet)
279     IR.getInstruction()->cycleEvent();
281   for (InstRef &IR : WaitSet)
282     IR.getInstruction()->cycleEvent();
291 bool Scheduler::mustIssueImmediately(const InstRef &IR) const {
292   const InstrDesc &Desc = IR.getInstruction()->getDesc();
301 bool Scheduler::dispatch(InstRef &IR) {
302   Instruction &IS = *IR.getInstruction();
307     IS.setLSUTokenID(LSU.dispatch(IR));
309   if (IS.isDispatched() || (IS.isMemOp() && LSU.isWaiting(IR))) {
310     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
311     WaitSet.push_back(IR);
315   if (IS.isPending() || (IS.isMemOp() && LSU.isPending(IR))) {
316     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR
318     PendingSet.push_back(IR);
323   assert(IS.isReady() && (!IS.isMemOp() || LSU.isReady(IR)) &&
333   if (!mustIssueImmediately(IR)) {
334     LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the ReadySet\n");
335     ReadySet.push_back(IR);