Lines Matching defs:PhysReg

218   void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
224       MCRegister PhysReg, const MachineInstr &MI) const;
321                                              MCRegister PhysReg) const {
360     MBB->addLiveIn(PhysReg, LaneMask);
375     // assigned PhysReg must be marked as live-in to those blocks.
376     MCRegister PhysReg = VRM->getPhys(VirtReg);
377     if (!PhysReg) {
385       addLiveInsForSubRanges(LI, PhysReg);
395           MBB->addLiveIn(PhysReg);
401   // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
562 /// defining block for a register assignment for a subregister def. \p PhysReg
566     MCRegister PhysReg, const MachineInstr &MI) const {
584       LRM->checkInterferenceLanes(BeforeMIUses, MIIndex.getRegSlot(), PhysReg);
588     dbgs() << "Need live out undef defs for " << printReg(PhysReg)
613         MCRegister PhysReg = VRM->getPhys(VirtReg);
614         if (!PhysReg)
617         assert(Register(PhysReg).isPhysical());
619         RewriteRegs.insert(PhysReg);
620         assert((!MRI->isReserved(PhysReg) ||
633                 (MO.isDef() && subRegLiveThrough(MI, PhysReg)))
634               SuperKills.push_back(PhysReg);
639                 SuperDeads.push_back(PhysReg);
641                 SuperDefs.push_back(PhysReg);
657                                                           PhysReg, MI);
675                     SuperDefs.push_back(TRI->getSubReg(PhysReg, SubIdx));
690           // PhysReg operands cannot have subregister indexes.
691           PhysReg = TRI->getSubReg(PhysReg, SubReg);
692           assert(PhysReg.isValid() && "Invalid SubReg for physical register");
697         MO.setReg(PhysReg);
724     for (Register PhysReg : RewriteRegs) {
725       for (MCRegUnit Unit : TRI->regunits(PhysReg)) {