Lines Matching defs:mi
158 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
164 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
166 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
169 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
787 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
789 MachineInstrSpan MIS(mi, MBB);
790 MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LV, LIS);
794 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
798 if (auto OldInstrNum = mi->peekDebugInstrNum()) {
799 assert(mi->getNumExplicitDefs() == 1);
803 unsigned OldIdx = mi->defs().begin()->getOperandNo();
812 MBB->erase(mi); // Nuke the old inst.
817 mi = NewMI;
818 nmi = std::next(mi);
908 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
915 MachineInstr *MI = &*mi;
1096 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1103 MachineInstr *MI = &*mi;
1166 make_range(mi, MachineBasicBlock::iterator(KillMI))) {
1211 MachineBasicBlock::iterator InsertPos = mi;
1308 /// Returns true if no copy needs to be inserted to untie mi's operands
1309 /// (either because they were untied, or because mi was rescheduled, and will
1313 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1318 MachineInstr &MI = *mi;
1346 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1363 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1376 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1420 MBB->insert(mi, NewMIs[0]);
1421 MBB->insert(mi, NewMIs[1]);
1435 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1492 mi = NewMIs[1];
1849 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1850 mi != me; ) {
1851 MachineBasicBlock::iterator nmi = std::next(mi);
1853 if (mi->isDebugInstr()) {
1854 mi = nmi;
1858 // Expand REG_SEQUENCE instructions. This will position mi at the first
1860 if (mi->isRegSequence())
1861 eliminateRegSequence(mi);
1863 DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1865 processCopy(&*mi);
1869 if (!collectTiedOperands(&*mi, TiedOperands)) {
1870 removeClobberedSrcRegMap(&*mi);
1871 mi = nmi;
1877 LLVM_DEBUG(dbgs() << '\t' << *mi);
1888 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1889 Register DstReg = mi->getOperand(DstIdx).getReg();
1891 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1895 removeClobberedSrcRegMap(&*mi);
1896 mi = nmi;
1902 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1903 processStatepoint(&*mi, TiedOperands)) {
1905 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1906 mi = nmi;
1912 processTiedPairs(&*mi, TO.second, Dist);
1913 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1917 if (mi->isInsertSubreg()) {
1920 unsigned SubIdx = mi->getOperand(3).getImm();
1921 mi->removeOperand(3);
1922 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1923 mi->getOperand(0).setSubReg(SubIdx);
1924 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1925 mi->removeOperand(1);
1926 mi->setDesc(TII->get(TargetOpcode::COPY));
1927 LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1931 Register Reg = mi->getOperand(0).getReg();
1937 TRI->getSubRegIndexLaneMask(mi->getOperand(0).getSubReg());
1938 SlotIndex Idx = LIS->getInstructionIndex(*mi).getRegSlot();
1942 if (mi->getOperand(0).isUndef()) {
1965 removeClobberedSrcRegMap(&*mi);
1966 mi = nmi;