Lines Matching defs:RegB

141   bool regsAreCompatible(Register RegA, Register RegB) const;
150   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156   bool isProfitableToConv3Addr(Register RegA, Register RegB);
160                           Register RegB, unsigned &Dist);
545                                                   Register RegB) const {
546   if (RegA == RegB)
548   if (!RegA || !RegB)
550   return TRI->regsOverlap(RegA, RegB);
634                                                       Register RegB,
674     MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);
680     // -RegB is not tied to a register and RegC is compatible with RegA.
681     // -RegB is tied to the wrong physical register, but RegC is.
682     // -RegB is tied to the wrong physical register, and RegC isn't tied.
686     // -RegC is not tied to a register and RegB is compatible with RegA.
687     // -RegC is tied to the wrong physical register, but RegB is.
688     // -RegC is tied to the wrong physical register, and RegB isn't tied.
699   // If there is a use of RegB between its last def (could be livein) and this
702   if (!noUseAfterLastDef(RegB, Dist, LastDefB))
723   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))
770                                                         Register RegB) {
777   MCRegister FromRegB = getMappedReg(RegB, SrcRegMap);
788     Register RegA, Register RegB, unsigned &Dist) {
822   DstRegMap.erase(RegB);
1564   Register RegB = 0;
1573     // Grab RegB from the instruction because it may have changed if the
1575     RegB = MI->getOperand(SrcIdx).getReg();
1578     if (RegA == RegB) {
1587     assert(RegB.isVirtual() && "cannot make instruction into two-address form");
1604     MIB.addReg(RegB, 0, SubRegB);
1605     const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1614         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1652     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1660     if (RegA.isVirtual() && RegB.isVirtual())
1673       if (MO.getReg() == RegB) {
1689         LV->getVarInfo(RegB).removeKill(*MI)) {
1692       LV->addVirtualRegisterKilled(RegB, *PrevMI);
1696       SrcRegMap[LastCopiedReg] = RegB;
1713       LiveInterval &LI = LIS->getInterval(RegB);
1726       if (MO.getReg() == RegB) {
1735 //    RegA = STATEPOINT ... RegB(tied-def N)
1737 //    RegB = STATEPOINT ... RegB(tied-def N)
1738 // and replaces all uses of RegA with RegB.
1746     Register RegB = TO.first;
1758     assert(RegB == MI->getOperand(SrcIdx).getReg());
1760     if (RegA == RegB)
1769       const auto &UseLI = LIS->getInterval(RegB);
1772         LLVM_DEBUG(dbgs() << "LIS: " << printReg(RegB, TRI, 0)
1777     } else if (LV && LV->getVarInfo(RegB).findKill(MI->getParent()) != MI) {
1781       LLVM_DEBUG(dbgs() << "LV: " << printReg(RegB, TRI, 0)
1787     if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) {
1788       LLVM_DEBUG(dbgs() << "MRI: couldn't constrain" << printReg(RegB, TRI, 0)
1794     MRI->replaceRegWith(RegA, RegB);
1798       LiveInterval &LI = LIS->getInterval(RegB);
1815         LV->removeVirtualRegisterKilled(RegB, *MI);
1816       LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(RegB);
1821         LV->addVirtualRegisterKilled(RegB, *KillMI, false);