Lines Matching defs:DemandedElts
516 const APInt &DemandedElts,
523 if (DemandedBits.isZero() || DemandedElts.isZero())
527 if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
565 APInt DemandedElts = VT.isVector()
568 return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO);
641 const APInt &DemandedElts,
649 SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO);
667 APInt DemandedElts = VT.isFixedLengthVector()
670 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth,
676 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
689 if (DemandedBits == 0 || DemandedElts == 0)
693 unsigned NumElts = DemandedElts.getBitWidth();
711 Src, DemandedBits, DemandedElts, DAG, Depth + 1))
726 if (DemandedElts[j])
743 if (DemandedElts[i]) {
758 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts,
764 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
765 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
777 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
778 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
790 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
791 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
802 RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
806 LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
815 DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
819 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
830 DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
837 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
874 unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
890 if (IsLE && DemandedElts == 1 &&
906 !DemandedElts[CIdx->getZExtValue()])
918 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
933 if (M < 0 || !DemandedElts[i])
956 Op, DemandedBits, DemandedElts, DAG, Depth))
970 APInt DemandedElts = VT.isFixedLengthVector()
973 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG,
978 SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG,
981 return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG,
991 const APInt &DemandedElts, unsigned Depth) {
995 ConstantSDNode *N1C = isConstOrConstSplat(Op.getOperand(1), DemandedElts);
1014 if ((ConstOp = isConstOrConstSplat(Op2, DemandedElts)) &&
1021 if ((ConstOp = isConstOrConstSplat(Op3, DemandedElts)) &&
1046 unsigned NumSignedA = DAG.ComputeNumSignBits(ExtOpA, DemandedElts, Depth);
1047 unsigned NumSignedB = DAG.ComputeNumSignBits(ExtOpB, DemandedElts, Depth);
1050 DAG.computeKnownBits(ExtOpA, DemandedElts, Depth).countMinLeadingZeros();
1052 DAG.computeKnownBits(ExtOpB, DemandedElts, Depth).countMinLeadingZeros();
1152 APInt DemandedElts = OriginalDemandedElts;
1185 DemandedElts = APInt::getAllOnes(NumElts);
1200 if (!DemandedElts[0])
1212 if (DemandedElts == 1)
1219 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1236 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
1258 APInt DemandedVecElts(DemandedElts);
1264 if (!DemandedElts[Idx])
1295 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
1296 APInt DemandedSrcElts = DemandedElts;
1340 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
1368 DemandedElts.extractBits(NumSubElts, i * NumSubElts);
1384 if (!getShuffleDemandedElts(NumElts, ShuffleMask, DemandedElts, DemandedLHS,
1429 if (ConstantSDNode *RHSC = isConstOrConstSplat(Op1, DemandedElts)) {
1431 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
1440 DemandedElts, TLO))
1467 TLO.DAG.computeKnownBits(Op1, DemandedSub & DemandedElts, Depth + 1);
1478 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1481 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
1495 if (ShrinkDemandedConstant(Op, ~Known2.Zero & DemandedBits, DemandedElts,
1503 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) {
1505 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1507 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1522 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1528 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
1541 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1548 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) {
1550 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1552 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1595 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
1598 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
1618 ConstantSDNode *C = isConstOrConstSplat(Op1, DemandedElts);
1643 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
1668 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1672 if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) {
1674 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1676 Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1689 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts,
1692 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedElts,
1697 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1704 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts,
1707 if (SimplifyDemandedBits(Op.getOperand(1), DemandedBits, DemandedElts,
1715 if (SimplifyDemandedBits(Op.getOperand(3), DemandedBits, DemandedElts,
1718 if (SimplifyDemandedBits(Op.getOperand(2), DemandedBits, DemandedElts,
1723 if (ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
1763 TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
1775 TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
1815 InnerOp, DemandedElts, Depth + 2)) {
1833 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1846 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) {
1848 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
1919 if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO,
1933 TLO.DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
1936 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
1949 TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
1961 TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
1981 TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
2021 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
2030 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) {
2032 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
2041 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2047 TLO.DAG.getValidMaximumShiftAmount(Op, DemandedElts, Depth + 1)) {
2053 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
2061 DemandedElts, Depth + 1))
2074 if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >=
2086 TLO.DAG.getValidShiftAmount(Op, DemandedElts, Depth + 1)) {
2095 TLO.DAG.getValidShiftAmount(Op0, DemandedElts, Depth + 2)) {
2113 TLO.DAG.ComputeNumSignBits(Op0.getOperand(0), DemandedElts);
2132 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
2160 if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) {
2162 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
2172 DemandedElts, Depth + 1))
2184 if (ConstantSDNode *SA = isConstOrConstSplat(Op2, DemandedElts)) {
2190 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
2200 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
2203 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
2215 !DemandedElts.isAllOnes()) {
2217 Op0, Demanded0, DemandedElts, TLO.DAG, Depth + 1);
2219 Op1, Demanded1, DemandedElts, TLO.DAG, Depth + 1);
2233 if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts,
2246 if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1))
2249 if (ConstantSDNode *SA = isConstOrConstSplat(Op1, DemandedElts)) {
2256 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
2280 if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO,
2298 std::min(TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1),
2299 TLO.DAG.ComputeNumSignBits(Op1, DemandedElts, Depth + 1));
2305 KnownBits Known0 = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth + 1);
2306 KnownBits Known1 = TLO.DAG.computeKnownBits(Op1, DemandedElts, Depth + 1);
2342 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
2376 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
2391 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2402 TLO.DAG.ComputeMaxSignificantBits(Op0, DemandedElts, Depth + 1);
2426 if (SimplifyDemandedBits(Op0, InputDemandedBits, DemandedElts, Known, TLO,
2480 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2491 APInt InDemandedElts = DemandedElts.zext(InElts);
2517 APInt InDemandedElts = DemandedElts.zext(InElts);
2528 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2582 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2587 APInt InDemandedElts = DemandedElts.zext(InElts);
2607 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO,
2618 Src, TruncMask, DemandedElts, TLO.DAG, Depth + 1))
2647 TLO.DAG.getValidShiftAmount(Src, DemandedElts, Depth + 2);
2770 if (DemandedElts[j])
2791 if (DemandedElts[i]) {
2822 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
2833 ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1), DemandedElts);
2864 if (SimplifyDemandedBits(Op1, LoMask, DemandedElts, KnownOp1, TLO,
2867 DemandedElts, KnownOp0, TLO, Depth + 1) ||
2882 if (!LoMask.isAllOnes() || !DemandedElts.isAllOnes()) {
2884 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2886 Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2973 if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts,
2980 Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
3012 const APInt &DemandedElts,
3020 SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
3083 APInt DemandedElts = OriginalDemandedElts;
3084 unsigned NumElts = DemandedElts.getBitWidth();
3107 DemandedElts.setAllBits();
3110 if (DemandedElts == 0) {
3126 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts,
3128 SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts,
3141 if (!DemandedElts[0]) {
3181 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
3190 SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts);
3202 if (DemandedElts[i]) {
3222 if (DemandedElts[Elt])
3245 SrcDemandedElts = APIntOps::ScaleBitMask(DemandedElts, NumSrcElts);
3253 if (DemandedElts[i]) {
3265 if (TLO.DAG.isGuaranteedNotToBeUndefOrPoison(N0, DemandedElts,
3271 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && DemandedElts == 1)
3279 if (!DemandedElts.isAllOnes()) {
3286 if (!DemandedElts[i] && !Ops[i].isUndef()) {
3313 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
3323 if (!DemandedElts.isAllOnes()) {
3328 APInt SubElts = DemandedElts.extractBits(NumSubElts, i * NumSubElts);
3349 APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
3350 APInt DemandedSrcElts = DemandedElts;
3393 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
3403 if (!DemandedElts.isAllOnes()) {
3423 if (!DemandedElts[Idx])
3426 APInt DemandedVecElts(DemandedElts);
3439 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
3453 if (SimplifyDemandedVectorElts(Sel, DemandedElts, UndefSel, ZeroSel, TLO,
3458 APInt DemandedLHS(DemandedElts);
3459 APInt DemandedRHS(DemandedElts);
3474 APInt DemandedSel = DemandedElts & ~KnownZero;
3475 if (DemandedSel != DemandedElts)
3492 if (M < 0 || !DemandedElts[i])
3519 if (!DemandedElts[i] || (M < (int)NumElts && UndefLHS[M]) ||
3562 APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts);
3578 if (DemandedElts.isSubsetOf(KnownUndef))
3611 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3633 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
3637 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3646 if (!DemandedElts.isAllOnes())
3660 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
3664 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3673 if (!DemandedElts.isAllOnes())
3686 if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO,
3691 APInt DemandedElts0 = DemandedElts & ~SrcZero;
3702 if (DemandedElts.isSubsetOf(SrcZero | KnownZero | SrcUndef | KnownUndef))
3714 if (!DemandedElts.isAllOnes())
3722 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
3726 if (!DemandedElts.isAllOnes())
3728 Op.getOperand(0), DemandedElts, TLO.DAG, Depth + 1))
3733 if (DemandedElts.isSubsetOf(KnownUndef))
3742 if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
3749 if (SimplifyDemandedVectorEltsForTargetNode(Op, DemandedElts, KnownUndef,
3766 if (DemandedElts.isSubsetOf(KnownUndef))
3776 const APInt &DemandedElts,
3790 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
3823 GISelKnownBits &Analysis, Register R, const APInt &DemandedElts,
3829 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero,
3841 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3849 computeKnownBitsForTargetNode(Op, Known, DemandedElts, TLO.DAG, Depth);
3854 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3888 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
3900 return !canCreateUndefOrPoisonForTargetNode(Op, DemandedElts, DAG, PoisonOnly,
3909 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
3935 const APInt &DemandedElts,