Lines Matching defs:PredSU

401   SUnit *PredSU = PredEdge->getSUnit();
404   if (PredSU->NumSuccsLeft == 0) {
406     dumpNode(*PredSU);
411   --PredSU->NumSuccsLeft;
416     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());
421   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
422     PredSU->isAvailable = true;
424     unsigned Height = PredSU->getHeight();
428     if (isReady(PredSU)) {
429       AvailableQueue->push(PredSU);
433     else if (!PredSU->isPending) {
434       PredSU->isPending = true;
435       PendingQueue.push_back(PredSU);
823   SUnit *PredSU = PredEdge->getSUnit();
824   if (PredSU->isAvailable) {
825     PredSU->isAvailable = false;
826     if (!PredSU->isPending)
827       AvailableQueue->remove(PredSU);
830   assert(PredSU->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&
832   ++PredSU->NumSuccsLeft;
1973       SUnit *PredSU = Pred.getSUnit();
1974       if (SUNumbers[PredSU->NodeNum] == 0) {
1978           assert(It.SU != PredSU && "Trying to push an element twice?");
1982         WorkList.push_back(PredSU);
1996       SUnit *PredSU = Pred.getSUnit();
1997       unsigned PredSethiUllman = SUNumbers[PredSU->NodeNum];
2100     SUnit *PredSU = Pred.getSUnit();
2103     if (PredSU->NumRegDefsLeft == 0) {
2106     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2149     SUnit *PredSU = Pred.getSUnit();
2152     if (PredSU->NumRegDefsLeft == 0) {
2153       if (PredSU->getNode()->isMachineOpcode())
2157     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2192     SUnit *PredSU = Pred.getSUnit();
2195     if (PredSU->NumRegDefsLeft == 0) {
2210     // defs in PredSU. The can't be determined here, but we've already
2211     // compensated by reducing NumRegDefsLeft in PredSU during
2213     --PredSU->NumRegDefsLeft;
2214     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
2215     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
2274     SUnit *PredSU = Pred.getSUnit();
2277     if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2279     const SDNode *PN = PredSU->getNode();
2379     const SUnit *PredSU = Pred.getSUnit();
2380     if (PredSU->getNode() &&
2381         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
2383           cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
2450     SUnit *PredSU = Pred.getSUnit();
2451     if (PredSU->isVRegCycle) {
2452       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
2998     SUnit *PredSU = nullptr;
3001         PredSU = Pred.getSUnit();
3004     assert(PredSU);
3008     if (PredSU->hasPhysRegDefs)
3010     // Short-circuit the case where SU is PredSU's only data successor.
3011     if (PredSU->NumSuccs == 1)
3020     // Perform checks on the successors of PredSU.
3021     for (const SDep &PredSucc : PredSU->Succs) {
3024       // If PredSU has another successor with no data successors, for
3040         dbgs() << "    Prescheduling SU #" << SU.NodeNum << " next to PredSU #"
3041                << PredSU->NodeNum
3043     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
3044       SDep Edge = PredSU->Succs[i];
3048         Edge.setSUnit(PredSU);