Lines Matching defs:LRegs

1297                                SmallVectorImpl<unsigned> &LRegs,
1314       LRegs.push_back(*AliasI);
1320 /// by RegMask, and add them to LRegs.
1324                                      SmallVectorImpl<unsigned> &LRegs) {
1331       LRegs.push_back(i);
1348 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
1360                          RegAdded, LRegs, TRI);
1383               CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1395         CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI,
1414           LRegs.push_back(CallResource);
1420                                RegAdded, LRegs);
1432           CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1436       CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
1439   return !LRegs.empty();
1448       SmallVectorImpl<unsigned> &LRegs = LRegsPos->second;
1449       if (!is_contained(LRegs, Reg))
1475       SmallVector<unsigned, 4> LRegs;
1476       if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
1479                  if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource";
1480                  else dbgs() << printReg(LRegs[0], TRI);
1482       auto [LRegsIter, LRegsInserted] = LRegsMap.try_emplace(CurSU, LRegs);
1490         LRegsIter->second = LRegs;
1508     SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1514     for (unsigned Reg : LRegs) {
1559     SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
1560     assert(LRegs.size() == 1 && "Can't handle this yet!");
1561     unsigned Reg = LRegs[0];