Lines Matching defs:SrcVT

713   EVT SrcVT = LD->getMemoryVT();
714   TypeSize SrcWidth = SrcVT.getSizeInBits();
718   if (SrcWidth != SrcVT.getStoreSizeInBits() &&
726       (SrcVT != MVT::i1 ||
731     unsigned NewWidth = SrcVT.getStoreSizeInBits();
736     // way.  A zext load from NVT thus automatically gives zext from SrcVT.
751                            Result, DAG.getValueType(SrcVT));
756                            DAG.getValueType(SrcVT));
762     assert(!SrcVT.isVector() && "Unsupported extload!");
841                                  SrcVT.getSimpleVT())) {
869       if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
872         EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
873         if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) &&
874             (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
875              TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT))) {
879               (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
882                                         SrcVT, LD->getMemOperand());
884               ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
894         EVT SVT = SrcVT.getScalarType();
896           EVT ISrcVT = SrcVT.changeTypeToInteger();
910       assert(!SrcVT.isVector() &&
923                                       Chain, Ptr, SrcVT,
929                              Result, DAG.getValueType(SrcVT));
931         ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1793   EVT SrcVT = SrcOp.getValueType();
1798   if ((SrcVT.bitsGT(SlotVT) &&
1818   if (SrcVT.bitsGT(SlotVT))
1822     assert(SrcVT.bitsEq(SlotVT) && "Invalid store");
2550   EVT SrcVT = Op0.getValueType();
2554   if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64) &&
2626   if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) ||
2627       (SrcVT == MVT::i64 && DestVT == MVT::f64)) {
2643     EVT SetCCVT = getSetCCResultType(SrcVT);
2646         dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2648     EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout());
2650     SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
2651     SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
2652     SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
2653     SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
2659       SDValue InCvt = DAG.getSelect(dl, SrcVT, SignBitTest, Or, Op0);
2687   // The following optimization is valid only if every value in SrcVT (when
2689   // size of DestVT is >= than the number of bits in SrcVT -1.
2691              SrcVT.getSizeInBits() - 1 &&
2701   SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2702                                  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2712   switch (SrcVT.getSimpleVT().SimpleTy) {
3206     EVT SrcVT = Op.getValueType();
3208     if (SrcVT.getScalarType() == MVT::bf16) {
3213     if ((Tmp1 = EmitStackConvert(Op, SrcVT, DstVT, dl)))