Lines Matching defs:EltVT

390     EVT EltVT = Vec.getValueType().getVectorElementType();
391     if (Val.getValueType() == EltVT ||
392         (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
1955   EVT EltVT = VT.getVectorElementType();
1996         if (OpVT==EltVT)
1999           // If OpVT and EltVT don't match, EltVT is not legal and the
2003           CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2008         Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
3388     EVT EltVT = VT.getVectorElementType();
3391     if (!TLI.isTypeLegal(EltVT)) {
3392       EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3395       // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3397       if (NewEltVT.bitsLT(EltVT)) {
3399         // If original node was v4i64 and the new EltVT is i32,
3416         // EltVT gets smaller
3432       EltVT = NewEltVT;
3438         Ops.push_back(DAG.getUNDEF(EltVT));
3443         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3447             DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
5029                                         MVT EltVT, MVT NewEltVT) {
5030   unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
5582     MVT EltVT = OVT.getVectorElementType();
5593     assert(NewEltVT.bitsLE(EltVT) && "not handled");
5595     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5610     MVT EltVT = OVT.getVectorElementType();
5626     assert(NewEltVT.bitsLT(EltVT) && "not handled");
5628     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5650     Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
5654     MVT EltVT = OVT.getVectorElementType();
5672     assert(NewEltVT.bitsLT(EltVT) && "not handled");
5674     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5704     MVT EltVT = OVT.getVectorElementType();
5714     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);