Lines Matching defs:SRL
1607 else if (Opc == ISD::SRL)
1901 case ISD::SRL: return visitSRL(N);
2057 case ISD::SRL:
2486 BinOpcode == ISD::SRL) && Sel.hasOneUse()) {
2629 ShiftOp.getOpcode() != ISD::SRL)
2650 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT,
3924 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3927 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
4171 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
4927 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
5039 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5055 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
5127 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) &&
5225 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
5273 hasOperation(ISD::SRL, VT)) {
5280 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5295 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
5347 return DAG.getNode(ISD::SRL, DL, VT, X,
5531 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
5584 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
5974 // For binops SHL/SRL/SRA/AND:
5976 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
6528 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6873 InnerShift = ISD::SRL;
6874 else if (OuterShift == ISD::SRL)
6933 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse())
7017 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL ||
7428 return DAG.getNode(ISD::SRL, DL, VT, X,
7542 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
7569 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
7571 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
7612 // Make sure everything beyond the low halfword gets set to zero since the SRL
7637 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
7654 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
7659 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
7663 // SHL or SRL: look upstream for AND mask operand
7680 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
7694 if (Opc0 != ISD::SRL)
7716 } else { // Opc == ISD::SRL
7739 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
7775 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
7856 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
7980 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL &&
8203 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
8238 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL)
8252 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst &&
8277 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
8278 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
8534 if (IsBinOpImm(N1, ISD::SRL, 1) &&
8649 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
8670 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt);
8719 SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt);
9122 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) &&
9905 BinOpLHSVal.getOpcode() == ISD::SRL) &&
10160 N0.getOperand(0).getOpcode() == ISD::SRL) {
10181 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10213 if (N0.getOpcode() == ISD::SRL &&
10223 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff);
10224 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10345 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
10346 "SRL or SRA node is required here!");
10374 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
10579 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
10645 (N0.getOperand(0).getOpcode() == ISD::SRL ||
10669 // If the sign bit is known to be zero, switch this to a SRL.
10671 return DAG.getNode(ISD::SRL, DL, VT, N0, N1);
10704 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1}))
10722 if (N0.getOpcode() == ISD::SRL) {
10742 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
10747 N0.getOperand(0).getOpcode() == ISD::SRL) {
10762 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
10771 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
10800 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01);
10811 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1);
10812 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10826 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
10830 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0),
10844 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
10866 // could be set on input to the CTLZ node. If this bit is set, the SRL
10867 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
10868 // to an SRL/XOR pair, which is likely to simplify more.
10874 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
10886 return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
10916 // However when after the source operand of SRL is optimized into AND, the SRL
10990 ISD::SRL, DL, VT, N1,
11044 return DAG.getNode(ISD::SRL, DL, VT, N1, N2);
11250 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
11256 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
11288 if ((!LegalOperations || TLI.isOperationLegal(ISD::SRL, VT)) &&
11290 return DAG.getNode(ISD::SRL, DL, VT, X, Y);
11365 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) {
11370 if ((N0.getOpcode() == ISD::SRL &&
11463 if (Opcode != ISD::SRA && Opcode != ISD::SRL)
11477 case ISD::SRL:
12976 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) &&
13046 if (NewShiftOpc == ISD::SHL || NewShiftOpc == ISD::SRL) {
13438 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
13724 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
14405 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
14742 } else if (Opc == ISD::SRL || Opc == ISD::SRA) {
14743 // Another special-case: SRL/SRA is basically zero/sign-extending a narrower
14759 // Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD.
14760 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
14790 // In case Opc==SRL we've already prepared ExtVT/ExtType/ShAmt based on doing
14795 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) {
14796 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0;
14797 // Bail out when the SRL has more than one use. This is done for historical
14800 // case the SRL has multiple uses and we get here with Opc!=ISD::SRL?
14801 // FIXME: Can't we just skip this check for the Opc==ISD::SRL case.
14802 if (!SRL.hasOneUse())
14807 auto *LN = dyn_cast<LoadSDNode>(SRL.getOperand(0));
14808 auto *SRL1C = dyn_cast<ConstantSDNode>(SRL.getOperand(1));
14820 // Because a SRL must be assumed to *need* to zero-extend the high bits
14822 // lowering of SRL and an sextload.
14840 // If the SRL is only used by a masking AND, we may be able to adjust
14842 SDNode *Mask = *(SRL->user_begin());
14843 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND &&
14852 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT))
14861 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) {
14869 N0 = SRL.getOperand(0);
15045 if (N0.getOpcode() == ISD::SRL) {
15048 // We can turn this into an SRA iff the input to the SRL is already sign
15401 if (Src.getOpcode() == ISD::SRL && Src.getOperand(0)->hasOneUse()) {
15966 X = DAG.getNode(ISD::SRL, DL,
16080 // We currently avoid folding freeze over SRA/SRL, due to the problems seen
16081 // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
16083 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
18699 if (N.getOpcode() == ISD::SRL ||
18702 N.getOperand(0).getOpcode() == ISD::SRL))) {
18722 // SRL constant is equal to the log2 of the AND constant. The back-end is
19443 TLI.isOperationLegal(ISD::SRL, STType)) {
19444 Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val,
20087 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
20269 ISD::SRL, DL, IVal.getValueType(), IVal,
22948 case ISD::SRL:
23155 ISD::SRL, DL, XVT, X,
23529 if (In.getOpcode() != ISD::SRL) {
23537 // In is SRL
28012 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);